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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16504-3E
32-Bit Proprietary Microcontroller
CMOS
FR60 MB91350A Series
MB91F355A/F356B/355A/354A/V350A
DESCRIPTION
The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC CPU, incorporating a variety of I/O resources and bus control features for embedded control applications which require high CPU performance for This FR60 family is based on FR30 and FR40 families and enhanced is bus access. The FR60 family is a line of single-chip oriented microcontrollers incorporating a wealth of peripheral resources. The FR60 family is optimized for embedded control applications requiring high processing power of the CPU, such as DVD player, navigation, high performance Fax machine, and printer controls.
FEATURES
1. FR CPU
32-bit RISC, load/store architecture with a five-stage pipeline Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz) 16-bit fixed length instructions (basic instructions), 1 instruction per cycle Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift etc. * Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store instructions (Continued) * * * *
PACKAGE
176-pin plastic LQFP
(FPT-176P-M02)
I2C license Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
MB91350A Series
* Register interlock functions: Facilitating coding in assemblers * On-chip multiplier supported at the instruction level. Signed 32-bit multiplication: 5 cycles. Signed 16-bit multiplication: 3 cycles * Interrupt (PC, PS save): 6 cycles, 16 priority levels * Harvard architecture allowing program access and data access to be executed simultaneously * FR family instruction compatible
2. Bus Interface
* * * * * * * Maximum operating frequency: 25 MHz Capable of up to 24-bit address full output (16 MB of space) 8,16-bit data output Built-in pre-fetch buffer Non-used data and address pin are usable as general I/O port. Capable of chip-select signal output for completely independent four areas settable in 64 KB minimum Support for various memory interfaces: SRAM, ROM/Flash, page mode Flash ROM, page mode ROM Basic bus cycle: 2 cycles Programmable automatic wait cycle generator capable of inserting wait cycles for each area RDY input for external wait cycles Support for fly-by transfer for DMA, which enables wait control of independent I/O Memory ROM RAM (stack) RAM (executable) MB91V350A No 16 KB 16 KB MB91F355A 512 KB 16 KB 8 KB MB91F356B 256 KB 16 KB 8 KB MB91355A 512 KB 16 KB 8 KB MB91354A 384 KB 8 KB 8 KB
* * * *
3. Mounted Memory
4. DMAC (DMA Controller)
* Capable of simultaneous operation of up to 5 channels (3 channels for externalexternal operation) * Three transfer sources (external pin, internal peripheral, software) selectable by software. (Transfer can be started from UART0/1/2.) * Addressing using 32-bit full addressing mode (increment, decrement, fixed) * Transfer modes (demand transfer, burst transfer, step transfer, block transfer) * Support for fly-by transfer (between external I/O and memory) * Selectable transfer data size: 8, 16, or 32-bit * Multi-byte transfer enabled (by software) * DMAC descriptor in IO areas (200H to 240H, 1000H to 1024H)
5. Bit Search Module (for REALOS)
* Search for the position of the bit 1/0-changed first in 1 word from the MSB
6. Various Timers
* 4 channels of 16-bit reload timer (including 1 channel for REALOS): Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch3) * 16-bit free-running timer: 1 channel. Output compare module: 8 channels. Input capture module: 4 channels * 16-bit PPG timer 6 channels
7. UART
* UART Full duplex double buffer 5 channel * Selectable parity On/Off * Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable (Continued) 2
MB91350A Series
(Continued) * Internal timer for dedicated baud rate * External clock can be used as transfer clock * Assorted error detection functions (for parity, frame, and overrun errors) * 115 Kbps support
8. SIO
* 3 channels for 8-bit data serial transfer * Shift clock selectable from among internal three and external one * Shift direction selectable (transfer from LSB or MSB) selectable
9. Interrupt Controller
* Total of 17 external interrupt lines (1 nonmaskable interrupt pin and 16 normal interrupt pins available for Wake Up from STOP) * interrupt from internal peripheral * Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
10. D/A Converter
* 8-bit resolution. 3 channels
11. A/D Converter
* * * * 10-bit resolution. 12 channels Casting time for serial/parallel conversion: 1.48 s Conversion mode (single conversion mode, continuous conversion mode) Activation source (software, external trigger, peripheral interrupt)
12. Other Interval Timer/Counter
* 8/16-bit up/down counter * 16-bit PPG timer 5 channels * Watch dog timer
13. I2C Bus Interface (400 Kbps supported)
* 1channel master/slave sending and receiving * Arbitration and clock synchronization
14. I/O Port
* 3 V I/O ports (16 ports shared for external interrupts support 5 V input.) * Max 126 ports
15. Other Features
* Internal oscillator circuit as clock source, allowing PLL multiplication to be selected * Provided with INIT as a reset pin (The CPU operates without oscillation stabilization wait interval when the INIT pin is reset.) * others, watch-dog timer reset, software reset enable * Support for stop and sleep modes for low power consumption, capable of saving power during CPU operation at 32 kHz. * Gear function * Built-in time base timer * Package: LQFP-176 (lead pitch: 0.50 mm) * CMOS technology(0.35 m) * Power supply voltage: 3.3 V 0.3 V
3
4
MB91350A Series
PIN ASSIGNMENT
PG5/SCK5 NMI X1A VSS X0A MD2 MD1 MD0 X0 VCC X1 INIT VSS VCC PC0/DREQ2 PC1/DACK2 PC2/DSTP2/DEOP2 PB0/DREQ0 PB1/DACK0 PB2/DSTP0/DEOP0 PB3/DREQ1 PB4/DACK1 PB5/DSTP1/DEOP1 PB6/IOWR PB7/IORD PA0/CS0 PA1/CS1 PA2/CS2 PA3/CS3 VSS VCC P80/IN0/RDY P81/IN1/BGRNT P82/IN2/BRQ P83/RD P84/WR0 P85/IN3/WR1 P90/SYSCLK P91 P92/MCLK P93 P94/AS VSS VCC 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
(TOP VIEW)
(FPT-176P-M02)
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN5/PPG5 PN4/PPG4 PN3/PPG3 PN2/PPG2 PN1/PPG1 PN0/PPG0 VCC VSS PO7/OC7 PO6/OC6 PO5/OC5 PO4/OC4 PO3/OC3 PO2/OC2 PO1/OC1 PO0/OC0 PP3/TOT3 PP2/TOT2 PP1/TOT1 PP0/TOT0 VCC VSS AVSS/AVRL AVRH AVCC AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 DA2 DA1 DA0 DAVC DAVS
P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 VSS VCC P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS VCC P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 P65/A21 P66/A22 P67/A23 PG4/SO5 PG3/SI5 PG2/SCK4 PG1/SO4 PG0/SI4 PH5/SCK3 PH4/SO3 PH3/SI3 PH2/SCK2 PH1/SO2 PH0/SI2 PI5/SCK1 PI4/SO1 PI3/SI1 PI2/SCK0 PI1/SO0 PI0/SI0 VCC VSS PJ7/INT15 PJ6/INT14 PJ5/INT13 PJ4/INT12 PJ3/INT11 PJ2/INT10 PJ1/INT9 PJ0/INT8 PK7/INT7/ATG PK6/INT6/FRCK PK5/INT5 PK4/INT4 PK3/INT3 PK2/INT2 PK1/INT1 PK0/INT0 VCC VSS PL1/SCL PL0/SDA VSS PM5/SCK7/ZIN1/TRG5 PM4/SO7/BIN1/TRG4 PM3/SI7/AIN1/TRG3 PM2/SCK6/ZIN0/TRG2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
MB91350A Series
PIN DESCRIPTION
Pin no. 1 to 8 9 to 16 19 to 26 27 to 34 Pin name D16 to D23 P20 to P27 D24 to D31 P30 to P37 A00 to A07 P40 to P47 A08 to A15 P50 to P57 A16 to A20 37 to 41 P60 to P64 A21 to A23 42 to 44 47 to 48 49 P65 to P67 DA0, DA1 DA2 C G G D C Circuit type C C C C Description External data bus bit 16 to bit 23. Enabled in external bus mode. Available as a port in external bus 8-bit mode. external data bus bit 24 to bit 31. Enabled in external bus mode. Usable as port at single chip mode. Bits 0 to 7 of external address bus. Enabled in external bus mode. Usable as port at single chip mode. Bits 8 to 15 of external address bus. Enabled in external bus mode. Usable as port at single chip mode. Bits 16 to 20 of external address bus. Enabled in external bus mode. Available as a port either in single chip mode or with no external address bus in use. Bits 21 to 23 of external address bus. Enabled in external bus mode. Available as a port either in single chip mode or with no external address bus in use. D/A converter output pin. D/A converter output pin. Analog input pin. Analog input pin. Reload timer output port. This function is enabled when timer output is enabled. General purpose input/output port. This function is enabled when the timer output function is disabled. Output compare pin. D General purpose I/O. This function is available as a port when the output compare output is not in use. Output compare pin. D General purpose I/O. This function is available as a port when the output compare output is not in use. Output compare pin. D General purpose I/O. This function is available as a port when the output compare output is not in use. Output compare pin. D General purpose I/O. This function is available as a port when the output compare output is not in use. PPG timer output pin. D General purpose I/O. This function is available as a port when the PPG timer output is not in use. (Continued) 5
50 to 57 AN0 to AN7 58 to 61 AN8 to AN11
TOT0 to TOT3
67 to 70
PP0 to PP3 OC0
71
PO0 OC1
72
PO1 OC2
73
PO2
OC3 to OC7
74 to 78
PO3 to PO7 PPG0
81
PN0
MB91350A Series
Pin no.
Pin name PPG1
Circuit type PPG timer output pin. D
Description
82
PN1 PPG2
General purpose I/O. This function is available as a port when the PPG timer output is not in use. PPG timer output pin. General purpose I/O. This function is available as a port when the PPG timer output is not in use. PPG timer output pin. General purpose I/O. This function is available as a port when the PPG timer output is not in use. PPG timer output pin. General purpose I/O. This function is available as a port when the PPG timer output is not in use. PPG timer output pin. General purpose I/O. This function is available as a port when the PPG timer output is not in use. Data input for serial I/O6. Since this input is used as required when serial I/O 6 is in input operation, the port output must remain off unless intentionally turned on. 8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. External trigger input for PPG timer0. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use. Data output for serial I/O 6. This function is enabled when the serial I/O6 data output is enabled. 8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. External trigger input for PPG timer1. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use. Clock input/output for serial I/O 6. This function is enabled when serial I/O6 is using the external shift clock mode, or serial I/O5 clock output function is enabled. 8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. External trigger input for PPG timer2. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use. (Continued)
83
PN2 PPG3
D
84
PN3 PPG4
D
85
PN4 PPG5
D
86
PN5 SI6 AIN0
D
87 TRG0 PM0 SO6 BIN0 88 TRG1 PM1 SCK6 ZIN0 89 TRG2 PM2
D
D
D
6
MB91350A Series
Pin no.
Pin name
Circuit type
Description Data input for serial I/O 7. Since this input is used as required when serial I/O 7 is in input operation, the port output must remain off unless intentionally turned on.
SI7
90
AIN1 TRG3 PM3 SO7 BIN1
D
8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. External trigger input for PPG timer 3. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use. Data output for serial I/O 7. This function is enabled when the serial I/O 7 data output is enabled. 8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. External trigger input for PPG timer 4. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use. Clock input/output for serial I/O5. This function is enabled when serial I/O 7 is using the external shift clock mode, or serial I/O 5 clock output function is enabled. 8/16-bit up/down counter input. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. External trigger input for PPG timer 5. Since this input is used as required when enabled, the port output must remain off unless intentionally turned on. General purpose I/O. This function is available a port when the serial I/O, 8/16bit up/down counter, and PPG timer outputs are not in use. Clock input/output pin for I2C bus. This function is enabled when the I2C system is enabled for operation in standard mode. The port output must remain off unless intentionally turned on. (Open drain input) General purpose input/output port. This function is available as a port when the I2C system is disabled for operation. (Open drain input) Clock input/output pin for I2C bus. This function is enabled when the I2C system is enabled for operation in standard mode. The port output must remain off unless intentionally turned on. (Open drain input) General purpose input/output port. This function is available as a port when the I2C system is disabled for operation. (Open drain input) External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on. General purpose input/output port. (Continued)
91 TRG4 PM4 SCK7 ZIN1 92 TRG5 PM5
D
D
SDA 94 PL0 F
SCL 95 PL1 INT0 to INT5 PK0 to PK5 F
98 to 103
E
7
MB91350A Series
Pin no.
Pin name INT6
Circuit type
Description External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on.
104 FRCK PK6 INT7 105 ATG PK7 106 to 113 INT8 to INT15 PJ0 to PJ7 116 SI0 PI0 SO0 117 PI1 SCK0 118 PI2 SI1 PI3 SO1 120 PI4 SCK1 121 PI5
E
External clock input pin for freerun timer. Since this input is used as required when selected as the external clock input for the free running timer, the port output must remain off unless intentionally turned on. General purpose input/output port. External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on.
E
External trigger input for A/D converter. Since this input is used as required when selected as an A/D activation source, the port output must remain off unless intentionally turned on. General purpose input/output port. External interrupt input. Since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless intentionally turned on. General purpose input/output port. UART0 data input. Since this input is used as required when UART0 is in input operation, the port output must remain off unless intentionally turned on. General purpose input/output port. UART0 data output. This function is enabled when the UART0 data output is enabled. General purpose input/output port. This function is enabled when the data output function of UART0 is disabled. UART0 clock input/output pin. This function is enabled either when clock output enabled or when UART0 inputs the external clock signal. General purpose input/output port. This function is enabled when UART0 is not using the external clock signal with the UART0 clock output function disabled. UART1 data input. Since this input is used as required when UART1 is in input operation, the port output must remain off unless intentionally turned on. General purpose input/output port. UART1 data outpu. This function is enabled when the UART1 data output is enabled. General purpose input/output port. This function is enabled when the data output function of UART1 is disabled. UART1 clock input/output pin. This function is enabled either when clock output enabled or when UART1 inputs the external clock signal. General purpose input/output port. This function is enabled when UART1 is not using the external clock signal with the UART1 clock output function disabled. (Continued)
E
D
D
D
119
D
D
D
8
MB91350A Series
Pin no.
Pin name SI2 PH0 SO2
Circuit type D
Description UART2 data input. Since this input is used as required when UART2 is in input operation, the port output must remain off unless intentionally turned on. General purpose input/output port. UART2 data outpu. This function is enabled when the UART2 data output is enabled. General purpose input/output port. This function is enabled when the data output function of UART2 is disabled. UART2 clock input/output pin. This function is enabled either when the UART2 clock output is enabled or when UART2 inputs the external clock signal. General purpose input/output port. This function is enabled when UART2 is not using the external clock signal with the UART2 clock output function disabled. UART3 data input. Since this input is used as required when UART3 is in input operation, the port output must remain off unless intentionally turned on. General purpose input/output port. UART3 data outpu. This function is enabled when the UART3 data output is enabled. General purpose input/output port. This function is enabled when the data output function of UART3 is disabled. UART0 clock input/output pin. This function is enabled either when the UART3 clock output is enabled or when UART3 inputs the external clock signal. General purpose input/output port. This function is enabled when UART3 is not using the external clock signal with the UART3 clock output function disabled. UART4 data input. Since this input is used as required when UART4 is in input operation, the port output must remain off unless intentionally turned on. General purpose input/output port. UART4 data output. This function is enabled when the UART4 data output is enabled. General purpose input/output port. This function is enabled when the data output function of UART4 is disabled. UART4 clock input/output pin. This function is enabled either when the UART4 clock output is enabled or when UART4 inputs the external clock signal. General purpose input/output port. This function is enabled when UART4 is not using the external clock signal with the UART4 clock output function disabled. Data input for serial I/O5. Since this input is used as required when serial I/O5 is in input operation, the port output must remain off unless intentionally turned on. General purpose input/output port. Data output for serial I/O5. This function is enabled when the serial I/O5 data output is enabled. General purpose input/output port. This function is enabled when the I/O5 data output function is disabled. (Continued) 9
122
123 PH1 SCK2 124 PH2 SI3 PH3 SO3 126 PH4 SCK3 127 PH5 SI4 PG0 SO4 129 PG1 SCK4 130 PG2 SI5 PG3 SO5 132 PG4
D
D
125
D
D
D
128
D
D
D
131
D
D
MB91350A Series
Pin no.
Pin name
Circuit type
Description Clock innput/output for serial I/O5. This function is enabled when serial I/O5 is using the external shift clock mode, or serial I/O5 clock output function is enabled. General purpose input/output port. This function is enabled when serial I/O5 is not using the external shift clock mode with the serial I/O5 clock output function disabled. NMI (Non Maskable Interrupt) input Output clock cycle time. Sub clock Input clock cycle time. Sub clock 2 to 0Mode Pins. The levels applied to these pins set the basic operating mode. Connect VCC or VSS. Input circuit configuration: The production model (masked-ROM model) is type "H". The Flash ROM model is type "J". Input clock cycle time. Main clock Output clock cycle time. Main clock External reset input External input for DMA transfer requests. Since this input is used as required when selected as a DMA start source, the port output must remain off unless intentionally turned on. General purpose input/output port. External acknowledge output for DMA transfer requests. This function is enabled when the transfer request acceptance output for DMA is enabled. General purpose input/output port. This function is enabled when the transfer request acceptance output for DMA is enabled. Completion output for DMA external transfer. This function is enabled when the external transfer end output for DMA is enabled.
SCK5 133 PG5 134 135 137 NMI X1A X0A H B B D
138 to 140
MD2 to MD0
H, J
141 143 144
X0 X1 INIT DREQ2 PC0 DACK2
A A I
147
C
148 PC1 DEOP2 149 DSTP2 PC2
C
C
Stop input for DMA external transfer. This function is enabled when the external transfer stop input for DMA is enabled. General purpose input/output port. This function is enabled when the external transfer end output and external transfer stop input for DMA are disabled. External input for DMA transfer requests. Since this input is used as required when selected as a DMA start source, the port output must remain off unless intentionally turned on. General purpose input/output port. External acknowledge output for DMA transfer requests. This function is enabled when the transfer request acceptance output for DMA is enabled. General purpose input/output port. This function is enabled when the transfer request acceptance output for DMA is disabled. (Continued)
150
DREQ0 PB0 DACK0
C
151 PB1
C
10
MB91350A Series
Pin no.
Pin name DEOP0
Circuit type
Description Completion output for DMA external transfer. This function is enabled when the external transfer end output for DMA is enabled.
152
DSTP0 PB2
C
Stop input for DMA external transfer. This function is enabled when the external transfer stop input for DMA is enabled. General purpose input/output port. This function is enabled when the external transfer end output and external transfer stop input for DMA are disabled. External input for DMA transfer requests. Since this input is used as required when selected as a DMA start source, the port output must remain off unless intentionally turned on. General purpose input/output port. External acknowledge output for DMA transfer requests. This function is enabled when the transfer request acceptance output for DMA is enabled. General purpose input/output port. This function is enabled when the external transfer request acceptance output for DMA is disabled. Completion output for DMA external transfer. This function is enabled when the external transfer end output for DMA is enabled.
153
DREQ1 PB3 DACK1
C
154 PB4 DEOP1 155 DSTP1 PB5 IOWR 156 PB6 IORD 157 PB7 158 CS0 PA0 CS1 159 PA1 CS2 160 PA2
C
C
Stop input for DMA external transfer. This function is enabled when the external transfer stop input for DMA is enabled. General purpose input/output port. This function is enabled when the external transfer end output and external transfer stop input for DMA are disabled. Write strobe output for DMA fly-by transfer. This function is enabled when the DMA fly-by transfer write strobe output is enabled. General purpose input/output port. This function is enabled when the DMA fly-by transfer write strobe output is disabled. Read storobe output for DMA fly-by transfer. This function is enabled when the DMA fly-by transfer read strobe output is enabled. General purpose input/output port. This function is enabled when the DMA fly-by transfer read strobe output is disabled. Chip select 0 output. Enable at external bus mode General purpose input/output port. This is enabled at single chip mode. Chip select 1 output. This function is enabled when the chip select 1 output is enabled. General purpose input/output port. This function is enabled when the chip select 1 output is disabled. Chip select 2 output. This function is enabled when the chip select 2 output is enabled. General purpose input/output port. This function is enabled when the chip select 2 output is disabled. (Continued)
C
C
C
C
C
11
MB91350A Series
Pin no.
Pin name CS3
Circuit type
Description Chip select 3 output. This function is enabled when the chip select 3 output is enabled. General purpose input/output port. This function is enabled when the chip select 3 output is disabled. External ready input. The pin has this function when external ready input is enabled.
161 PA3 RDY 164 IN0 P80 BGRNT 165 IN1 P81 BRQ 166 IN2 P82 167 168 RD P83 WR0 P84 WR1 169 IN3 P85
C
D
Input capture input pin. Since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. General purpose input/output port. This function is enabled when external ready signal input is disabled. Acknowledge output for external bus release. Outputs "L" when the external bus is released. The pin has this function when output is enabled.
D
Input capture input pin. Since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. General purpose input/output port. This function is enabled when external bus release acknowledge output is disabled. External bus release request input. Input "1" to request release of the external bus. The pin has this function when input is enabled.
D
Input capture input pin. Since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. General purpose input/output port. The pin has this function when the external bus release request input is disabled.
D D
External bus read strobe output. It is available in the external bus mode. General purpose input/output port. This is enabled at single chip mode. External bus write strobe output. It is available in the external bus mode. General purpose input/output port. This is enabled at single chip mode. External bus write strobe output. This function is enabled when WR1 output is enabled in external bus mode.
D
Input capture input pin. Since this input is used as required when selected as an input capture input, the port output must remain off unless intentionally turned on. General purpose input/output port. The pin has this function when the external bus write-enable output is disabled. System clock output The pin has this function when system clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop mode.) General purpose input/output port. The pin has this function when system clock output is disabled.
SYSCLK 170 P90 171 P91 C C
General purpose input/output port. (Continued)
12
MB91350A Series
(Continued) Pin no. Pin name Circuit type Description Memory clock output. This function is enabled when the memory clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in sleep/stop mode.) General purpose input/output port. This function is enabled when the memory clock output is disabled. C General purpose input/output port. Address strobe output. This function is enabled when address strobe output is enabled. General purpose input/output port. This function is enabled when address load output is disabled.
MCLK 172 P92 173 P93 AS 174 P94 C C
* Power supply and GND pins Pin no. 17, 35, 65, 79, 93, 96, 114, 136, 145, 162, 175 18, 36, 66, 80, 97, 115, 142, 146, 163, 176 45 46 62 63 64 Pin name VSS VCC DAVS DAVC AVCC AVRH AVSS/AVRL Description GND pins. Apply equal potential to all of the pins. 3.3 V power supply pin. Apply equal potential to all of the pins. GND pin for D/A converter Power supply pin for D/A converter Analog power supply pin for A/D converter Reference power supply pin for A/D converter Analog GND pin for A/D converter
13
MB91350A Series
I/O CIRCUIT TYPE
Type
X1
Circuit type
Remarks * Oscillation feedback resistance: approx. 1 M Clock input
A
X0
Standby control
* Oscillation feedback resistance for low speed (subclock oscillation): approx. 7 M
X1A
Clock input
B
X0A
Standby control
Pull-up control Digital output With standby control C Digital output With Pull-up control Pull-up resistance = approx. 50 k (Typ) IOL = 8 mA Pull-up control Digital output With standby control D Digital output With Pull-up control Pull-up resistance = approx. 50 k (Typ) IOL = 4 mA (Continued) * CMOS level output * CMOS level hysteresis input * CMOS level output * CMOS level input
Digital input
Standby control
Digital input
Standby control
14
MB91350A Series
Type
Circuit type
Remarks * CMOS level output * CMOS level hysteresis input
Digital output E Digital output
With stand voltage of 5 V IOL = 4 mA * Nch open drain output * CMOS level hysteresis input
Digital input
Digital output F Digital input with standby control With stand voltage of 5 V IOL = 15 mA * Analog input with switch
Standby control
G Analog input
Control
* CMOS level hysteresis input
H
Digital input * CMOS level hysteresis input
with pull-up resistor I Pull-up resistance = approx. 50 k (Typ) Digital input (Continued) 15
MB91350A Series
(Continued) Type Circuit type Remarks * CMOS level input * Flash product only
J Control signal Mode input Diffused resistor
16
MB91350A Series
HANDLING DEVICES
* Preventing Latchup
Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latchup,if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating.
* Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor.
* About power supply pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to an external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device.
* About Crystal oscillator circuit
Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the circuit board so that X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout.
* Notes on Using External Clock
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode(oscillator stop mode) must not be used. (This is because the X1 pin stops at High level output in STOP mode.) Using an external clock (normal)
X0
X1
Note: STOP mode (oscillation stop mode) cannot be used.
* Clock control block
Take the oscillation stabilization wait time during Low level input to the INIT pin.
17
MB91350A Series
* Notes on not using the sub clock
When no oscillator is connected to the X0A and X1A pins, pull down the X0A pin and open the X1A pin.
X0
OPEN
X1
MB91350A
* Treatment of NC and OPEN pins
Pins marked as NC and OPEN must be left open-circuit.
* Mode pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low.
* Operation at start-up
The INIT pin must be at Low level when the power supply is turned on. Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling time required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)
* About oscillation input at power on
When turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state.
* Caution on Operations during PLL Clock Mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the PLL's internal self-oscillating oscillator circuit. Performance of this operation, however, cannot be guaranteed.
* External bus setting
This model guarantees an external bus frequency of 25 MHz. Setting the base clock frequency to 50 MHz with DIVR1 (external bus base clock division setting register) initialized sets the external bus frequency also to 50 MHz. Before changing the base clock frequency, set the external bus frequency not exceeding 25 MHz.
* MCLK and SYSCLK
MCLK and SYSCLK has a difference that MCLK stops in SLEEP/STOP mode but SYSCLK stops only in STOP mode. Use either depending on each application. Upon initialization, MCLK becomes invalid (PORT) and SYSCLK becomes valid. To use MCLK, set the port function register (PFR) to select the use of that clock.
* Pull-up control
Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the " ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4) Normal Bus Access Read/Write Operation, (5) Multiplex Bus Access Read/Write operation and (7) Hold Timing". Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby mode. 18
MB91350A Series
* Sub clock select
Immediately after switching from main clock mode to subclock mode for the clock source, insert at least one NOP instruction. (ldi #0x0b, r0) (ldi #_CLKR, r12) stb r0, @r12 // sub-clock mode nop // Must insert NOP instruction
* Bit Search Module
The BSD0, BSD1, and BDSC registers are accessed only in words.
* D-bus memory
Do not allocate the code area in memory on the D-bus because no instruction fetch takes place to the D-bus. Executing an instruction fetch to the D-bus area causes wrong data to be interpreted as code, possibly letting the device to run out of control.
* Low Power Consumption Mode
To enter the sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing to it. Precisely, use the following sequence. Set the I flag, ILM, and ICR to, after returning from standby mode, branch to the interrupt handler having caused the device to return. (ldi #value_of_standby, r0) (ldi #_STCR, r12) stb r0, @r12 // set STOP/SLEEP bit ldub @r12, r0 // Must read STCR // after reading, go into standby ldub @r12, r0 mode nop // Must insert NOP *5 nop nop nop nop
* Switch shared port function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR). Note, however, that bus pins are switched depending on external bus settings.
* Pre-fetch
When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only. Byte or halfword access results in wrong data read.
* I/O port access
Ports are accessed only in bytes.
* Built-in RAM
Immediately after a reset is canceled, the internal RAM allocation restricting function is still working, allowing only 4 KB to be used for data and for program execution irrespective of the on-chip RAM capacity. 19
MB91350A Series
* Flash memory
In programming mode, Flash memory cannot be used as an interrupt vector table. A reset is possible.
* Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. 1. The following operations are performed when the instruction followed by a DIVOU/DIVOS instruction results in: (a) acceptance of a user interrupt or NMI, (b) single-stepping, or (c) a break at a data event or emulator menu. * The D0 and D1 flags are updated in advance. * An EIT handling routine (user interrupt, NMI, or emulator) is executed. * Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1). 2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed. * The PS register is updated in advance. * An EIT handling routine (user interrupt, NMI, or emulator) is executed. * Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1).
20
MB91350A Series
[Note on debugger]
* Step execution of RETI command
If an interrupt occurs frequently during single-stepping, the corresponding interrupt handling routine is executed repeatedly. This will prevent the main routine and low-interrupt-level programs from being executed. (Whenever RETI is single-stepped when interrupts by the timebase timer have been enabled, for example, the timebase timer routine causes a break at the beginning.) Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debugging.
* Break function
If the address at which to cause a hardware break (including a event break) is set to the address currently contained in the system stack pointer or in the area containing the stack pointer, the user program causes a break after execution of one instruction. To prevent this, do not set (word) access to the area containing the address in the system stack pointer as the target of a hardware break (including an event break).
* Internal ROM area
Do not set an area of internal ROM as a DMAC transfer destination.
* Simultaneous occurrences of a software break (INTE instruction) and a user interrupt/NMI
When an INTE instruction and a user interrupt/NMI are accepted simultaneously, the emulator debugger reacts as follows. The emulator debugger stops while indicating a location in the user program, which is not a user-specified breakpoint. (It stops with the beginning of the user interrupt/NMI handling routine indicated.) The user program cannot be re-executed correctly. To prevent this problem, follow the instructions below. When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as follows. * The debugger stops pointing to a location other than the programmed breakpoints. * The halted program is not re-executed correctly. If this symptom occurs, use a hardware break in place of a hardware break. When using a monitor debugger, do not set a break at the relevant location. * A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer.
21
MB91350A Series
BLOCK DIAGRAM
FR CPU
32
32
Bit search
RAM (Stack)
ROM/Flash RAM (Executable) Bus Converter
32 32
DMAC 5 channels
DREQ0 to DREQ2 DACK0 to DACK2 DEOP0/DSTP0 to DEOP2/DSTP2 IOWR IORD
A23 to A00 D31 to D16 RD WR1, WR0 RDY BRQ BGRNT SYSCLK
X0, X1 MD0 to MD2 INIT X0A, X1A
Clock control
Clock timer
Interrupt DMAC (DMA Controller)
32 16 Adapter
External memory I/F
16
PORT I/F
PORT
6 channels PPG 4 channels reload timer 16-bit free-run timer 4 channels input capture 8 channels output compare
TRG0 to TRG5 PPG0 to PPG5
INT0 to INT15 NMI SI0 to SI4 SO0 to SO4 SCK0 to SCK4
16 channels External interrupt
5 channels UART
TOT0 to TOT3
FRCK
5 channels U-Timer
IN0 to IN3
SI5 to SI7 SO5 to SO7 SCK5 to SCK7
3 channels SIO
OC0 to OC7
AN0 to AN11 ATG AVRH, AVCC AVSS/AVRL DA0 to DA2 DAVC, DAVS
12 channels A/D 1 channel I2C
SDA SCL
3 channels D/A
2 channels 8/16-bit up/down counter
AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1
ROM/Flash RAM (Stack) RAM (Executable)
MB91F355A 512 KB (Flash) 16 KB 8 KB
MB91F356B 256 KB (Flash) 16 KB 8 KB
MB91355A 512 KB 16 KB 8 KB
MB91354A 384 KB 16 KB 8 KB
22
MB91350A Series
CPU AND CONTROL UNIT
Internal architecture The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced instructions for embedded controller applications.
1. Features
* * * * RISC architecture employed. Basic instructions: Executed at 1 instruction per cycle General-purpose registers: 32-bit x 16 registers 4GB linear memory space Multiplier integrated. 32-bit x 32-bit multiplication: 5 cycles. 16-bit x 16-bit multiplication: 3 cycles Enhanced interrupt servicing. Fast response speed (6 cycles). Multiple interrupts supported. Level masking (16 levels) Enhanced I/O manipulation instructions. Memory-to-memory transfer instructions, Bit manipulation instructions High code efficiency. Basic instruction word length: 16-bit Low-power consumption. Sleep mode and stop mode Gear function
*
* * * *
23
MB91350A Series
2. Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. The 32-bit/16-bit bus converter is connected to a 32-bit bus (F-bus), providing an interface between the CPU and peripheral resources. The Harvard-Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller.
FR CPU D-bus I-bus
32 I address 32 I data D address 32 Princeton bus converter External data 16 Harvard External address 24
Data RAM
D data
32
Address 32-bit 16-bit bus converter Data
32
32
16
R-bus
F-bus
Peripherals resource
Internal I/O
bus controller
24
MB91350A Series
3. Programming model
* Basic programming model
32-bit Initial Value:
R0 R1 XXXX XXXXH
GENERAL PURPOSE REGISTERS
R12 R13 R14 R15
AC FP SP
XXXX XXXXH 0000 0000 H
Program counter program status Table base register Return pointer System stack pointer User stack pointer Multiplication and division result register
PC PS TBR RP SSP USP MDH MDL
ILM
SCR
CCR
25
MB91350A Series
4. Register
General purpose registers
32-bit Initial Value:
R0 R1 XXXX XXXXH
R12 R13 R14 R15
AC FP SP
XXXX XXXXH 0000 0000 H
Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory access pointers for CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced. R13 : Virtual accumulator R14 : frame pointer R15 : Stack pointer The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 0000 0000H (SSP value).
* PS (Program Status)
This register holds the program status and is divided into the ILM, SCR, and CCR. The undefined bits in the following illustration are all reserved bits. Reading these bits always returns "0". Writing to them has no effect. Bit position 31
20 16 10 87 0
ILM
SCR
CCR
PS
26
MB91350A Series
* CCR (Condition Code Register )
7 6 5 S 4 I 3 N 2 Z 1 V 0 C
Initial Value: - - 00XXXXB
CCR S I N Z V C : Stack flag. Cleared to "0" by a reset. : Interrupt enable flag. Cleared to "0" by a reset. : Negative flag. The initial value after a reset is indeterminate. : Zero flag. The initial value after a reset is indeterminate. : Overflow flag. The initial value after a reset is indeterminate. : Carry flag. The initial value after a reset is indeterminate.
* SCR (System Condition code Register )
10 D1 9 D0 8 T
Initial Value: XX0B
SCR Flag for step dividing Stores intermediate data for stepwise multiplication operations. Step trace trap flag A flag specifying whether the step trace trap function is enabled or not. Emulator use step trace trap function. The function cannot be used by the user program when using the emulator.
* ILM
20 19 18 17 16
Initial Value: 01111B
ILM4 ILM3 ILM2 ILM1 ILM0
ILM This register stores the interrupt level mask value. The value in the ILM register is used as the level mask. Initialized to "15" (01111B) by a reset.
* PC (Program Counter)
31 PC 0
Initial Value: XXXXXXXXH
PC The program counter contains the address of the instruction currently being executed. The initial value after a reset is indeterminate.
27
MB91350A Series
* TBR (Table Base Register)
31 TBR 0
Initial Value: 0 0 0 FFC0 0H
TBR The table base register contains the start address of the vector table used for servicing EIT events. The initial value after a reset is 000FFC00H
* RP (Return Pointer)
31 RP 0
Initial Value: XXXXXXXXH
RP The return pointer contains the address to which to return from a subroutine. When the CALL instruction is executed, the value in the PC is transferred to the RP . When the RET instruction is executed, the value in the RP is transferred to the PC. The initial value after a reset is indeterminate.
* SSP (System Stack Pointer)
31 SSP 0
Initial Value: 0 0 0 0 0 0 0 0H
SSP The SSP is the system stack pointer and functions as R15 when the S flag is "0". The SSP can be explicitly specified. The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event occurs. The initial value after a reset is 00000000H
* USP (User Stack Pointer)
31 USP 0
Initial Value: XXXXXXXXH
USP The USP is the user stack pointer and functions as R15 when the S flag is "1". The SSP can be explicitly specified. The initial value after a reset is indeterminate. This pointer cannot be used by the RETI instruction.
28
MB91350A Series
* Multiply & Divide registers
31 MDH MDL 0
Multiplication and division result register These registers hold the results of a multiplication or division. Each of them is 32-bit long. The initial value after a reset is indeterminate.
29
MB91350A Series
MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed. Mode Pins MD2 MD1 MD0 0 0 0 0 0 1 Mode name Internal ROM mode vector External ROM mode vector Reset vector access area Internal External The bus width is specified by the mode register. Remarks
Values other than those listed in the table are prohibited.
2. Mode Register (MODR)
The data written to the mode register at 000F FFF8H using mode vector fetch is called mode data. After an operation mode has been set in the mode register (MODR), the device operates in the operation mode. The mode register is set by any reset source. User programs cannot write data to the mode register. Note : Conventionally the FR family has nothing at addresses (0000 07FFH) in the mode register. MODR 000F FFF8H
7 0 6 0 5 0 4 0 3 0 2 ROMA 1 WTH1 0 WTH0
Initial Value XXXXXXXXB
Operation mode setting bits
[bit 7 to bit 3] Reserved bit Be sure to set this bit to "00000". Operation is not guaranteed when any value other than "00000" is set. [bit 2] ROMA (internal ROM enable bit) The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas. ROMA 0 1 function External ROM mode Remarks Internal F-bus RAM is valid; the area (80000H to 100000H) of internal ROM is used as an external area.
Internal ROM mode Internal F-bus RAM and F-bus ROM become valid.
30
MB91350A Series
[bit 1, bit 0] WTH1, WTH0 (Bus width setting bits) Used to set the bus width to be used in external bus mode. When the operation mode is the external bus mode, this value is set in bits BW1 and BW0 in AMD0 (CS0 area). WTH1 0 0 1 1 WTH0 0 1 0 1 function 8-bit bus width 16-bit bus width single chip mode External bus mode Setting disabled single chip mode Remarks
31
MB91350A Series
MEMORY SPACE
1. Memory space
The FR family has 4 GB of logical address space (232 addresses) available to the CPU by linear access.
* Direct Addressing Areas
The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The size of directly addressable areas depends on the length of the data being accessed as shown below. byte data access : 000H to 0FFH half word data access : 000H to 1FFH word data access : 000H to 3FFH
2. Memory Map
* Memory map of MB91F355A/MB91355A Single chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0003 E000H I/O I/O I/O I/O
Internal ROM external bus mode
External ROM external bus mode Direct addressing area Refer to "3. I/O Map"
Access disallowed
Built-in RAM 8 KB (Executable)
Access disallowed Built-in RAM 8 KB (Executable)
Built-in RAM 16 KB (Stack)
Access disallowed
Built-in RAM 8 KB (Executable) Built-in RAM 16 KB (Stack)
0004 0000H
Built-in RAM 16 KB (Stack)
0004 4000H 0005 0000H 0008 0000H
Access disallowed
Access disallowed
Access disallowed
External area Built-in RAM 512 KB
Built-in RAM 512 KB
0010 0000H
External area
Access disallowed
FFFF FFFFH
External area
* Each mode is set depending on the mode vector fetch after INIT is negated. * The MB91V350A uses the area of 512 KB of internal ROM as emulation RAM in the MB91355A memory map. The internal RAM (Instruction) has been expanded from 8 KB to 16 KB. * The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the available area is updated, the instruction must be followed by at least 1 NOP instruction. 32
MB91350A Series
* Memory Map of MB91354A
Single chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0003 E000H
Built-in RAM 8 KB (Executable)
Internal ROM external bus mode
I/O I/O
External ROM external bus mode
I/O I/O
Direct addressing area Refer to "3. I/O Map"
Access disallowed
Access disallowed
Built-in RAM 8 KB (Executable) Built-in RAM 8 KB (Stack)
Access disallowed
Built-in RAM 8 KB (Executable) Built-in RAM 8 KB (Stack)
0004 0000H
Built-in RAM 8 KB (Stack)
0004 2000H 0005 0000H 0008 0000H 000A 0000H
Access disallowed
Access disallowed
Access disallowed
External area
Access disallowed
Built-in ROM 384 KB Access disallowed
Built-in ROM 384 KB External area
External area
0010 0000H
FFFF FFFFH
* Each mode is set depending on the mode vector fetch after INIT is negated. * The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the available area is updated, the instruction must be followed by at least 1 NOP instruction.
33
MB91350A Series
* Memory Map of MB91356B
Single chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0003 E000H
Built-in RAM 8 KB (Executable)
Internal ROM external bus mode
I/O I/O
External ROM external bus mode
I/O I/O
Direct addressing area Refer to "3. I/O Map"
Access disallowed
Access disallowed
Built-in RAM 8 KB (Executable) Built-in RAM 16 KB (Stack)
Access disallowed
Built-in RAM 8 KB (Executable) Built-in RAM 16 KB (Stack)
0004 0000H
Built-in RAM 16 KB (Stack)
0004 4000H 0005 0000H 0008 0000H 000C 0000H
Access disallowed
Access disallowed
Access disallowed
External area
Access disallowed
Built-in ROM 256 KB Access disallowed
Built-in ROM 256 KB External area
External area
0010 0000H
FFFF FFFFH
* Each mode is set depending on the mode vector fetch after INIT is negated. * The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the available area is updated, the instruction must be followed by at least 1 NOP instruction.
34
MB91350A Series
3. I/O Map
This shows the location of the various peripheral resource registers in the memory space. (How to read the table) Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Address 000000H
Block diagram T-unit Port Data Register
Read/write attribute, Access unit (B : Byte, H : Half Word, W : Word) Initial value after a reset Register name (First-column register at address 4n, second-column register at address 4n + 2) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : "1" : Initial value is "1". "0" : Initial Value: "0". "X" : Initial value is "X". "-" : No physical register at this location
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H 000024H
Register +0 PDR4 [R/W] B XXXXXXXX PDR8 [R/W] B - - XXXXXX PDRC [R/W] B - - - - - XXX PDRG[R/W] B - - XXXXXX PDRK [R/W] B XXXXXXXX PDRO [R/W] B XXXXXXXX PDRH [R/W] B - - XXXXXX PDRL [R/W] B - - - - - - XX PDRP [R/W] B - - - - XXXX SES5 [R/W] B*3 - - - - - - 00 SDR5 [R/W] B*3 XXXXXXXX +1 PDR5 [R/W] B XXXXXXXX PDR9 [R/W] B - - - XXXXX +2 PDR2 [R/W] B XXXXXXXX PDR6 [R/W] B XXXXXXXX PDRA [R/W] B - - - - XXXX PDRI [R/W] B - - XXXXXX PDRM [R/W] B - - XXXXXX PDRJ [R/W] B XXXXXXXX PDRN [R/W] B - - XXXXXX +3 PDR3 [R/W] B XXXXXXXX PDRB [R/W] B XXXXXXXX
Block diagram
T-unit Port Data Register
R-bus Port Data Register
Reserved SIO 5*3 (Continued) 35
SMCS5 [R/W] B, H*3 00000010 - - - - 00 - -
MB91350A Series
Address 000028H 00002CH 000030H 000034H 000038H 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H
Register +0 +1 +2 SES6 [R/W] B - - - - - - 00 SES7 [R/W] B - - - - - - 00 CDCR5 [R/W] B 0---1111 CDCR7 [R/W] B 0 - - - 1111 SRCL6 [W] B ------- +3 SDR6 [R/W] B XXXXXXXX SDR7 [R/W] B XXXXXXXX *1 *1 SRCL7 [W] B ------- SMCS6 [R/W] B, H 00000010 - - - - 00 - SMCS7 [R/W] B, H 00000010 - - - - 00 - CDCR6 [R/W] B 0 - - - 1111 *1 SRCL5 [W] B -------
Block diagram SIO 6 SIO 7 SIO Prescaler 5 SIO Prescaler 6, 7 SIO5 to SIO7 Reserved Ext int (INT0 to INT7) DLYI/I-unit
EIRR0 [R/W] B, H, W ENIR0 [R/W] B, H, W 00000000 00000000 DICR [R/W] B, H, W HRCL [R/W] B, H, W -------0 0 - - 11111 TMRLR [W] H, W XXXXXXXX XXXXXXXX TMRLR [W] H, W XXXXXXXX XXXXXXXX TMRLR [W] H, W XXXXXXXX XXXXXXXX SSR [R/W] B, H, W 00001000 SIDR/SODR [R/W] B, H, W XXXXXXXX
ELVR0 [R/W] B, H, W 00000000 TMR [R] H, W XXXXXXXX XXXXXXXX TMCSR [R/W] B, H, W - - - - 0000 00000000 TMR [R] H, W XXXXXXXX XXXXXXXX TMCSR [R/W] B, H, W - - - - 0000 00000000 TMR [R] H, W XXXXXXXX XXXXXXXX TMCSR [R/W] B, H, W - - - - 0000 00000000 SCR [R/W] B, H, W SMR [R/W] B, H, W 00000100 00 - - 0 - - DRCL [W] B -------UTIMC [R/W] B 0 - - 00001
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0 U-Timer/ UART 0 UART1 U-Timer/ UART 1 UART2 U-Timer/ UART 2 (Continued)
UTIM [R] H (UTIMR [W] H) 00000000 00000000 SSR [R/W] B, H, W 00001000 SIDR/SODR [R/W] B, H, W XXXXXXXX
SCR [R/W] B, H, W SMR [R/W] B, H, W 00000100 00 - - 0 - - DRCL [W] B -------UTIMC [R/W] B 0 - - 00001
UTIM [R] H (UTIMR [W] H) 00000000 00000000 SSR [R/W] B, H, W 00001000 SIDR/SODR [R/W] B, H, W XXXXXXXX
SCR [R/W] B, H, W SMR [R/W] B, H, W 00000100 00 - - 0 - - DRCL [W] B -------UTIMC [R/W] B 0 - - 00001
UTIM [R] H (UTIMR [W] H) 00000000 00000000
36
MB91350A Series
Address 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H
Register +0 +1 +2 +3 ADCS2 [R/W]B, H, W ADCS1 [R/W]B, H, W X000XX00 000X0000 ADTH0 [R] B, H, W XXXXXXXX ADTH2 [R] B, H, W XXXXXXXX IBCR [R/W] B, H, W 00000000 ADTL0 [R] B, H, W 000000XX ADTL2 [R] B, H, W 000000XX ADCT [R/W] H, W XXXXXXXX_XXXXXXXX ADTH1 [R] B, H, W XXXXXXXX ADTH3 [R] B, H, W XXXXXXXX ADTL1 [R] B, H, W 000000XX ADTL3 [R] B, H, W 000000XX
Block diagram
A/D converter: Successive approximation
DACR2 [R/W] B, H, W DACR1 [R/W] B, H, W DACR0 [R/W] B, H, W -------0 -------0 -------0
D/A Converter DADR2 [R/W] B, H, W DADR1 [R/W] B, H, W DADR0 [R/W] B, H, W XXXXXXXX XXXXXXXX XXXXXXXX IBSR [R] B, H, W 00000000 *1 Reserved Reserved
ITBA [R/W] B, H, W - - - - - - 00 00000000 ISMK [R/W] B, H, W 01111111 ICCR [R/W] B, H, W 0 - 011111 *1 ISBA [R/W] B, H, W - 0000000 IDBL [R/W] B, H, W -------0 *1 *1 Reserved I2C interface
ITMK [R/W] B, H, W 00 - - - - 11 11111111 IDAR [R/W] B, H, W 00000000 *1 *1
TMRLR [W] H, W XXXXXXXX XXXXXXXX RCR1 [W] B, H, W 00000000 RCR0 [W] B, H, W 00000000
TMR [R] H, W XXXXXXXX XXXXXXXX TMCSR [R/W] B, H, W - - - - 0000 00000000 UDCR1 [R] B, H, W 00000000 SCR [R/W] B, H, W 00000100 SCR [R/W] B, H, W 00000100 UDCR0 [R] B, H, W 00000000
Reload Timer 3
CCRH0 [R/W] B, H, W CCRL0 [R/W] B, H, W 0000B4H 00001000 00001000 0000B8H 0000BCH 0000C0H CCRH1 [R/W] B, H, W CCRL1 [R/W] B, H, W 00001000 00001000 SSR [R/W] B, H, W 00001000 SIDR/SODR [R/W] B, H, W XXXXXXXX
8/16-bit CSR0 [R/W] B, H, W Up/Down Counter 00000000 0, 1 CSR1 [R/W] B, H, W 00000000 SMR [R/W] B, H, W 00 - - 0 - - UTIMC [R/W] B 0 - - 00001 SMR [R/W] B, H, W 00 - - 0 - - Reserved UART3 U-Timer/ UART 3 UART4 (Continued) 37
0000C4H
UTIM [R] H (UTIMR [W] H) 00000000 00000000 SSR [R/W] B, H, W 00001000 SIDR/SODR [R/W] B, H, W XXXXXXXX
0000C8H
MB91350A Series
Address 0000CCH 0000D0H
Register +0 +1 +2 +3 UTIMC [R/W] B 0 - - 00001 UTIM [R] H (UTIMR [W] H) 00000000 00000000 EIRR1 [R/W] B, H, W ENIR1 [R/W]B, H, W 00000000 00000000 TCDT [R/W] H, W 00000000 00000000 IPCP1 [R] H, W XXXXXXXX XXXXXXXX IPCP3 [R] H, W XXXXXXXX XXXXXXXX ICS23 [R/W] B, H, W 00000000
Block diagram U-Timer/ UART 4 Ext int (INT8-15) 16-bit Free run Timer
ELVR1 [R/W] B, H, W 00000000 TCCS [R/W] B, H, W 00000000
0000D4H
0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H to 000114H 000118H 00011CH 000120H 000124H 000128H 00012CH
IPCP0 [R] H, W XXXXXXXX XXXXXXXX IPCP2 [R] H, W XXXXXXXX XXXXXXXX ICS01 [R/W] B, H, W 00000000 16-bit ICU
OCCP1 [R/W] H, W XXXXXXXX XXXXXXXX OCCP3 [R/W] H, W XXXXXXXX XXXXXXXX OCCP5 [R/W] H, W XXXXXXXX XXXXXXXX OCCP7 [R/W] H, W XXXXXXXX XXXXXXXX OCS23 [R/W] B, H, W 1110110 00001100 OCS67 [R/W] B, H, W 1110110 00001100
OCCP0 [R/W] H, W XXXXXXXX XXXXXXXX OCCP2 [R/W] H, W XXXXXXXX XXXXXXXX OCCP4 [R/W] H, W XXXXXXXX XXXXXXXX OCCP6 [R/W] H, W XXXXXXXX XXXXXXXX OCS01 [R/W] B, H, W 1110110 00001100 OCS45 [R/W] B, H, W 1110110 00001100 PCSR0 [W] H, W XXXXXXXX_XXXXXXXX PCNH0 [R/W] B, H, W PCNL0 [R/W] B, H, W 00000000 00000000 PCSR1 [W] H, W XXXXXXXX_XXXXXXXX PCNH1 [R/W] B, H, W PCNL1 [R/W] B, H, W 00000000 00000000 GCN20 [R/W] B 00000000 Reserved Reserved PPG Control 0 Reserved 16-bit OCU *3
GCN10 [R/W] H 00110010_00010000 PTMR0 [R] H, W 11111111_11111111 PDUT0 [W] H, W XXXXXXXX_XXXXXXXX PTMR1 [R] H, W 11111111_11111111 PDUT1 [W] H, W XXXXXXXX_XXXXXXXX
PPG0
PPG1
(Continued) 38
MB91350A Series
Address 000130H 000134H 000138H 00013CH 000140H 000144H 000148H 00014CH 000150H to 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H
Register +0 +1 +2 +3 PTMR2 [R] H, W 11111111_11111111 PDUT2 [W] H, W XXXXXXXX_XXXXXXXX PTMR3 [R] H, W 11111111_11111111 PDUT3 [W] H, W XXXXXXXX_XXXXXXXX PTMR4 [R] H, W 11111111_11111111 PDUT4 [W] H, W XXXXXXXX_XXXXXXXX PTMR5 [R] H, W 11111111_11111111 PDUT5 [W] H, W XXXXXXXX_XXXXXXXX PCSR2 [W] H, W XXXXXXXX_XXXXXXXX PCNH2 [R/W] B, H, W PCNL2 [R/W] B, H, W 00000000 00000000 PCSR3 [W] H, W XXXXXXXX_XXXXXXXX PCNH3 [R/W] B, H, W PCNL3[R/W] B, H, W 00000000 00000000 PCSR4 [W] H, W XXXXXXXX_XXXXXXXX PCNH4 [R/W] B, H, W PCNL4 [R/W] B, H, W 00000000 00000000 PCSR5 [W] H, W XXXXXXXX_XXXXXXXX PCNH5 [R/W] B, H, W PCNL5 [R/W] B, H, W 00000000 00000000 DMACA0 [R/W] B, H, W*2 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] B, H, W*2 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] B, H, W*2 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] B, H, W*2 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] B, H, W*2 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] B, H, W 00000000 00000000 XXXXXXXX XXXXXXXX
Block diagram
PPG2
PPG3
PPG4
PPG5
Reserved
DMAC
(Continued) 39
MB91350A Series
Address 00022CH to 00023CH 000240H 000244H to 00027CH 000280H 000284H to 00038CH 000390H 000394H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH
Register +0 +1 DMACR [R/W] B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX FRLR [R/W] B, H, W - - - - - - 01*3 DRLR [R/W] B, H, W - - - - - - 01*3 BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDRG[R/W] B - - 000000 DDRK [R/W] B 00000000 DDRO [R/W] B 00000000 PFRG [R/W] B - - 00 - 00 ________ PFRO [R/W] B 00000000 DDRH [R/W] B - - 000000 DDRL [R/W] B - - - - - - 00 DDRP [R/W] B - - - - 0000 PFRH [R/W] B - - 00 - 00 PFRL [R/W] B - - - - - - 00 PFRP [R/W] B - - - - 0000 PFRI [R/W] B - - 00 - 00 PFRM [R/W] B - - 00 - 00 PFRN [R/W] B - - 000000 DDRI [R/W] B - - 000000 DDRM [R/W] B - - 000000 DDRJ [R/W] B 00000000 DDRN [R/W] B - - 000000 +2 +3
Block diagram Reserved
DMAC
Reserved F-bus RAM capacity limit Reserved D-bus RAM capacity limit Reserved
Bit Search Module
R-bus Data Direction Register
R-bus Port Function Register
Reserved (Continued)
40
MB91350A Series
Address 000420H 000424H 000428H 00042CH to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H
Register +0 PCRG [R/W] B - - 000000 PCRO [R/W] B 00000000 +1 PCRH [R/W] B - - 000000 PCRP [R/W] B - - - - 0000 ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W - - - 11111 - - - 11111 - - - 11111 - - - 11111 RSRR [R/W] B, H, W STCR [R/W] B, H, W TBCR [R/W] B, H, W 10000000 00110011 00XXXX00 CLKR [R/W] B, H, W 00000000 WPR [W] B, H, W XXXXXXXX CTBR [W] B, H, W XXXXXXXX +2 PCRI [R/W] B - - 000000 PCRM [R/W] B - - 000000 +3 PCRN [R/W] B - - 000000
Block diagram
R-bus Pull-up Control Register
Reserved
Interrupt Control unit
Clock DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W Control unit 00000011 00000000 OSCCR [R/W] B XXXXXXX0 (Continued) 41
MB91350A Series
Address 00048CH 000490H 000494H 000498H 00049CH to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH 000630H to 00063CH 000640H 000644H 000648H
Register +0 WPCR [R/W] B 00 - - - 000 OSCR [R/W] B 000 - - XX0 RSTOP0 [W] B 00000000 +1 RSTOP1 [W] B 00000000 DDR4 [R/W] B 00000000 DDR8 [R/W] B - - 000000 DDRC [R/W] B - - - - - 000 PFR8 [R/W] B --1--0-PFRB2 [R/W] B 00 - - - - 00 PCR4 [R/W] B 00000000 PCR8 [R/W] B --000000 PCRC [R/W] B -----000 PFR9 [R/W] B - - - 010 - 1 PFRC [R/W] B - - - 00000 PCR5 [R/W] B 00000000 PCR9 [R/W] B 00000000 ASR0 [R/W] H, W 00000000 00000000 ASR1 [R/W] H, W 00000000 00000000 ASR2 [R/W] H, W 00000000 00000000 ACR0 [R/W] B, H, W 1111XX00 00000000 ACR1 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR2 [R/W] B, H, W XXXXXXXX XXXXXXXX DDR5 [R/W] B 00000000 DDR9 [R/W] B - - - 00000 DDR2 [R/W] B 00000000 DDR6 [R/W] B 00000000 DDRA [R/W] B - - - - 0000 PFR6 [R/W] B 11111111 PFRA [R/W] B - - - - 1111 PCR2 [R/W] B 00000000 PCR6 [R/W] B 00000000 PCRA [R/W] B 00000000 PFRB1 [R/W] B 00000000 PCR3 [R/W] B 00000000 PCRB [R/W] B 00000000 DDR3 [R/W] B 00000000 DDRB [R/W] B 00000000 +2 RSTOP2 [W] B 00000000 +3 RSTOP3 [W] B - - - - - 000
Block diagram Clock timer Main oscillation stabilization timer Peripheral stop control Reserved Reserved
T-unit Data Direction Register
T-unit Port Function Register
T-unit Pull-up Control Register
Reserved
T-unit
(Continued) 42
MB91350A Series
Address 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H to 000AFCH 000B00H 000B04H 000B08H
Register +0 +1 +2 +3 ASR3 [R/W] H, W 00000000 00000000 ASR4 [R/W] H, W 00000000 00000000 ASR5 [R/W] H, W 00000000 00000000 ASR6 [R/W] H, W 00000000 00000000 ASR7 [R/W] H, W 00000000 00000000 AWR0 [R/W] B, H, W 01111111 11111111 AWR2 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR4 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR6 [R/W] B, H, W XXXXXXXX XXXXXXXX IOWR0 [R/W] B, H, W IOWR1 [R/W] B, H, W IOWR2 [R/W] B, H, W XXXXXXXX XXXXXXXX XXXXXXXX CSER [R/W] B, H, W 00000001 ESTS0 [R/W] X0000000 ECTL0 [R/W] 0X000000 ECNT0 [W] XXXXXXXX ESTS1 [R/W] XXXXXXXX ECTL1 [R/W] 00000000 ECNT1 [W] XXXXXXXX ESTS2 [R] 1XXXXXXX ECTL2 [W] 000X0000 EUSA [W] XXX00000 ECTL3 [R/W] 00X00X11 EDTC [W] 0000XXXX TCR [W] B, H, W 0000XXXX ACR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR4 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR5 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR6 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR7 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR1 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR3 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR5 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR7 [R/W] B, H, W XXXXXXXX XXXXXXXX
Block diagram
T-unit
Reserved
DSU (Evaluation chip only)
(Continued)
43
MB91350A Series
Address 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H
Register +0 +1 +2 EDTR1 [W] XXXXXXXX XXXXXXXX EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX +3 EWPT [R] 00000000 00000000 EDTR0 [W] XXXXXXXX XXXXXXXX
Block diagram
DSU (Evaluation chip only)
(Continued) 44
MB91350A Series
Address 000B64H 000B68H 000B6CH 000B70H to 000BFCH 000C00H 000C04H to 000C14H 000C18H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 001FFCH
Register +0 +1 +2 +3 EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register access disallowed
Block diagram
DSU (Evaluation chip only)
Reserved Interrupt Control unit R-bus test
Register access disallowed
DMASA0 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA0 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA1 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA1 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA2 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA2 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA3 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA3 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA4 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA4 [R/W] W XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
Reserved
DMAC
Reserved (Continued)
45
MB91350A Series
(Continued) Address 007000H 007004H 007008H 00700CH 007010H 007014H to 0070FFH *1 : Test register access barred *2 : The lower 16-bit (DTC(15: 0)) of DMACA0 to DMACA4 cannot be accessed in byte. *3 : The available area of internal RAM is restricted by the function described in 6-209 immediately after a reset is canceled. When the setting of the available area is updated, the instruction must be followed by at least 1 NOP instruction. Register +0 FLCR [R/W] 0110X000 FLWC [R/W] 00010011 +1 +2 +3 Reserved Flash memory Block diagram
46
MB91350A Series
VECTOR TABLE
Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART(Reception completed) UART(Reception completed) UART(Reception completed) UART0 (RX completed) UART1 (RX completed) UART2 (RX completed) Interrupt number 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Interrupt level 15 (FH) fixed15 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH RN 6 7 11 8 9 10 0 1 2 3 4 5
(Continued) 47
MB91350A Series
Interrupt source DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A/D I2C UART4 (Reception completed) SIO 5 SIO 6 SIO 7 UART3 (Reception completed) UART3 (RX completed) Reload timer 3/main oscillation stabilization wait timer Timebase timer overflow External interrupt: FPINT(8-15) Clock counter U/D Counter0 U/D Counter1 PPG 0/1 PPG 2/3 PPG 4/5 16-bit free-run timer ICU2/3 (capture) ICU1 (capture)/UART4 (transmission complete) ICU0 (capture) OCU0/1 (match) OCU2/3 (match) OCU4/5 (match) OCU6/7 (match) Interrupt delay source bit System reserved (Used by REALOS) System reserved (Used by REALOS)
Interrupt number 10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 16 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41
Interrupt level ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H
TBR default address 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H
RN 15 12 13 14
(Continued) 48
MB91350A Series
(Continued) Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt number 10 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 16 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Offset 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default address 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H RN
49
MB91350A Series
PERIPHERAL RESOURCES
1. Interrupt controller
(1)Description The interrupt controller manages interrupt reception and arbitration.
* Hardware configuration
This module consists of the following components: * ICR register * Interrupt priority determination circuit * Interrupt level and interrupt number (vector) generator * HOLD request cancellation request generator
* Main function
This module has the following major functions: * Detect NMI and interrupt requests * Prioritize interrupts (according to level and number) * Notify interrupt level of selected interrupt request (to CPU) * Notify interrupt number of selected interrupt request (to CPU) * Request (to the CPU) to return from stop mode in response to an NMI or interrupt request with interrupt level other than "11111" * Hold request cancellation request issued to the bus master
(2)Register list ICR register ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
(Continued) 50
MB91350A Series
(Continued) 7 6 5 4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Hold request cancel request resister (HRCL) HRCL 7 MHALT1 6 5 4 LVL4 3 LVL3 2 LVL2 1 LVL1 0 LVL0
51
MB91350A Series
(3)Block diagram
UNMI
WAKEUP ("1"
when LEVEL 11111)
Determine order of priority
5 NMI NMI LEVEL4 to LEVEL0
LEVEL determination
RI00 ICR00
VECTOR determination
6
LEVEL, VECTOR Generation
HLDREQ Cancel NMI request
MHALTI
VCT5 to VCT0
R-bus
52
MB91350A Series
2. External interrupt/NMI control
(1)Description The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to INT15. The level can be selected from "H", "L", rising edge, or falling edge (except for NMI). (2)Register list External interrupt enable register (ENIR)
7 EN7 6 EN6 5 EN5 4 EN4 3 EN3 2 EN2 1 EN1 0 EN0
External interrupt request register (EIRR)
15 ER7 14 ER6 13 ER5 12 ER4 11 ER3 10 ER2 9 ER1 8 ER0
Request level setting register (ELVR)
15 LB7 7 LB3 14 LA7 6 LA3 13 LB6 5 LB2 12 LA6 4 LA2 11 LB5 3 LB1 10 LA5 2 LA1 9 LB4 1 LB0 8 LA4 0 LA0
The above registers (for 8 channels) are available in two sets; there are a total of 16 channels.
(3)blockdiagram
R-bus 8
Interrupt enable register
Request F/F Edge detection circuit
17 INT0 to INT15 NMI
Interrupt request
17
Gate
8
Interrupt source register
16
Interrupt level setting register
53
MB91350A Series
3. REALOS-related Hardware
REALOS-related hardware is used by the real-time OS. Therefore, REALOS-related hardware cannot be used by user programs when REALOS is used. * Delay interrupt module (1)Description The delayed interrupt module generates a task switching interrupt. This module enables software to issue or cancel an interrupt request to the CPU. (2)Register list Delayed Interrupt Control Register (DICR) 7 6 5 4 3 2 1 0 DLY1
(3)Block diagram
R-bus
DLYI
Interrupt request
54
MB91350A Series
* Bit Search Module (1)Description The bit search module searches data written to an input register for "0", "1", or a change point and returns the detected bit position. (2)Register list 31 0 detection data register (BSD0) 1 detection data register (BSD1) Data register for transition detection (BSDC) Detection result register (BSRR) 0
(3)Block diagram
D-bus
Input latch
Address decoder
Detection mode
Creating 1 detection data
Bit search circuit
Search results
55
MB91350A Series
4. 8/16-bit up/down counter
(1)Description This block is the up/down counter consisting of 6 event input pins, an 8/16-bit up/down counter, an 8-bit reload/ compare register, and their control circuit. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 2 channels of 8/16-bit up/down counter in this block. This module has the following features. * 8-bit count register enabling counting from (0)d to (255)d (enabling counting from (0)d to (65535)d in "16-bit x 1 operation mode" ). * Four different count modes available with selectable count clocks Count mode Timer mode Up/down counter mode Phase difference count mode (2 multiplication) Phase difference count mode (4 multiplication) * Capable of selecting a count clock signal in timer mode, from among the inputs from two internal clocks and an internal circuit Count clock (When operating at 25 MHz ) Detection edge 80 ns (12.5 MHz : 2-frequency division) 320 ns (3.125 Hz : 8-frequency division) Falling Edge detection Rising Edge detection Detection at rising edge, falling edge, or both edges Edge detection disabled * Phase difference count mode suitable for counting for an encoder such as a motor, capable of easily counting the rotation angle and the number of revolutions at high precision by inputting the phase-A, phase-B, and phase-Z outputs of the encoder * ZIN pin available for two functions selectable (valid in all modes) ZIN Pin Counter clear function Gate function * Compare and reload functions available not only separately but also in combination for up/down counting at an arbitrary width Compare/reload function Compare function (comparison interrupt request output) Compare function (comparison interrupt request output and counter clear) Reload function (underflow interrupt request output and reload) Compare/reload function(Comparison interrupt request output and counter clear; underflow interrupt request output and reload) Compare/reload disabled * Count direction flag used to identify the preceding count direction * Capable of controlling the independent generations of interrupts at a compare match, reload (underflow), overflow, or at a count direction change 56
* Capable of selecting the detection edge of the external pin input signal in up/down counter mode
MB91350A Series
(2)Register list * Up/down count resister (UDCR) Up/down count resister ch0 (UDCR0)
7 D07 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00
Up/down count resister ch1 (UDCR1)
15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D09 8 D08
* Reload compare resister (RCR) Reload compare resister ch0 (RCR0)
7 D07 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00
Reload compare resister ch1 (RCR1)
15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D09 8 D08
* Counter status register (CSR) Counter status register ch(0, 1) (CSR0, 1)
7 CST 6 CIT 5 UDI 4 CM 3 OVF 2 UD 1 UD 0 UD
* Counter control resister (CCRL) Counter control resister ch(0, 1) (CCRL0, 1)
7
Reserved
6 CTU
5 UC
4 RLD
3 UD
2 CGS
1 CGE
0 CGE
* Counter control resister (CCRH) Counter control resister ch0 (CCRH0)
15 M16 14 CDC 13 CFI 12 CLK 11 CM 10 CM 9 CES 8 CES
* Counter control resister ch1 (CCRH1)
15
Reserved
14 CDC
13 CFI
12 CLK
11 CM
10 CM
9 CES
8 CES
57
MB91350A Series
(3)Block diagram
Data bus
8 bit CGE CGE CGS
RCR0(Reload compare register ch0
CTU
M16
To ch1
ZIN0, ZIN1
Edge/level detection
Reload control
RLD
Carry
UC
UD
Counter clear
8 bit
CES CM
CES CM
UDCR0(up/down counter register ch0
CM UD OVF
AIN0, AIN1 BIN0, BIN1
Up/down count clock select Prescaler
Count Clock
CST UD UD CDC
UDI
CIT
CLK
CFI
Interrupt output
58
MB91350A Series
5. 16-bit Reload Timer
(1)Description The 16-bit timer consists of a 16-bit down counter, 16-bit reload register, internal clock, clock generation prescaler, and control register. The clock source can be selected from among three internal clocks (prepared by frequency dividing the machine clock by 2/8/32, and also by 64/128 only for ch3) and an external event. The interrupt can be used to initiate DMA transfer. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 4 channels of this timer. (2)Register list Control status register (TMCSR)
15 14 13
Reserved
12 CSL2
11 CSL1
10 CSL0
9
8
Reserved Reserved
(ch3 only)
7
Reserved
6
5 OUTL
4 RELD
3 INTE
2 UF
1 CNTE
0 TRG
16-bit timer register(TMR)
15 0
16-bit reload register(TMRLR)
15 0
59
MB91350A Series
(3)Block diagram
16 7
16-bit reload register (TMRLR)
Reload
16
16-bit timer register (TMR) UF
RELD OUTL
Count enable
R | b u s CSL2
OUT CTL.
INTE UF IRQ
Re-trigger
CNTE TRG
Clock selector
CSL1 CSL0
External timer output (TOT0 to TOT3)
3 21 2
3
EXCK 2
5
IN CTL.
TOE0 to 3
Bit in PFRP
26
27
Prescaler clear
(ch3 only) Machine clock input
60
MB91350A Series
6. PPG (Programable Pulse Generator)
The PPG can efficiently output highly precise PWM waveforms. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 6 channels of PPG timer. (1)Description Each channel consists of a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty ratio setting buffer, and pin control unit. The count clocks for the 16-bit down counter can be selected from the following 4 types :(peripheral clock , / 4, /16, /64) The counter is initialized to "FFFFH" at a reset or counter borrow. PPG outputs (PPG0 to PPG5) are provided for each channel. (2)Register list 15 General control register 10 (GCN10) General control register 20 (GCN20) Timer register (PTMR0 to 5) Cycle setting register (PCSR0 to 5) Duty setting register (PDUT0) 0
(3)Block diagram (overall configuration for 1 channel) 16-bit reload timer ch0 TRG input PPG timer ch0 TRG input PPG timer ch1 TRG input PPG timer ch2
4 PPG0
16-bit reload timer ch1 General D/A control ICR register 10 (resource select) General D/A control ICR register 20
PPG1
PPG2
External TRG0 to TRG3
TRG input PPG timer ch3
PPG3
External TRG4
TRG input PPG timer ch4
PPG4
External TRG5
TRG input PPG timer ch5
PPG5
61
MB91350A Series
7. U-Timer (16-bit timer for UART baud rate generation)
(1) Description The U-Timer is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set depending on the combination of the chip operating frequency and U-Timer reload value. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5 channels of this timer. (2) Register list 15 U-Timer Register (UTIM) Reload Register (UTIMR) U-Timer Control Register (UTIMC) 87 0
(3) Block diagram
15 UTIMR (reload register) load 15 UTIM (U-timer)
0
0
clock
(Peripheral clock)
underflow control
f.f.
to UART
62
MB91350A Series
8. UART
(1) Description The UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module has the features listed below. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5 channels of UART. * * * * * * * * * Full duplex double buffer Asynchronous (start-stop synchronized) or CLK synchronized transmission Supports multi-processor mode Completely programmable baud rate. Arbitrary baud rate set by built-in timer (See the section for "U-Timer".) Variable baud rate can be input from an external clock. Error detection functions(parity, framing, overrun) Transmission signal format is NRZ UART Ch0 to Ch2 can start DMA transfer using interrupts (Ch3 and Ch4 cannot start DMA transfer). Capable of clearing DMAC interrupt source by writing to DRCL register
(2)Register list Serial input register/serial output register (SIDR/SODR)
7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Serial status register(SSR)
7 PE 6 ORE 5 FRE 4 RDRF 3 TDRE 2 BDS 1 RIE 0 TIE
Serial mode register
7 MD1 6 MD0 5 4 3 CS0 2 1 0
Serial control register(SCR)
7 PEN 6 P 5 SBL 4 CL 3 A/D 2 REC 1 RXE 0 TXE
DECL register (DRCL)
7 6 5 4 3 2 1 0
63
MB91350A Series
(3) Block diagram Control signal RX interrupt (to CPU) SCK (clock) From U-Timer
Transmission clock
External clock SCK SI (Receive data)
Clock selection circuit
Reception clock
TX interrupt (to CPU) Transmission control circuit Transmission start circuit Sending bit Counter Sending parity Counter SO (Send data)
Reception control circuit
Start bit detection circuit Received bit Counter Received parity Counter
Receive status decision circuit
RX shifter
RX complete
SIDR
TX shifter
Start transmission
SODR
For DMA received error generating signal (to DMAC)
R - bus
MD1 MD0
SMR Register
CS0
SCR Register
PEN P SBL CL A/D REC RXE TXE
SSR Register
PE ORE FRE RDRF TDRE BDS RIE TIE
Control signal
64
MB91350A Series
9. Extended I/O Serial Interface (SIO)
(1) Description This block is a serial I/O interface that allows data transfer using clock synchronization. It is composition of a single 8-bit x 1 channel. LSB-first or MSB-first transfer mode can be selected for data transfer. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 3 channels of this SIO. The serial I/O interface operates in 2 modes: * Internal shift clock mode: Transfer data in synchronization with the internal clock. * External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK). By manipulating the general-purpose port sharing the external pin (SCK) in this mode, data can also be transferred by a CPU instruction.
(2) Register list Serial mode control status register (SMCS)
15 SMD2 7 14 SMD1 6 13 SMD0 5 12 SIE 4 11 SIR 3 MODE 10 BUSY 2 BDS 9 STOP 1 8 STRT 0
SIO test resister(SES)
15 14 13 12 11 10 9 TST1 8 TST0
SDR (Serial Data Register)
7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
SIO prescaler control register (CDCR)
15 MD 14 13 12 11 DIV3 10 DIV2 9 DIV1 8 DIV0
DMAC interrupt source clear register (SRCL)
7 6 5 4 3 2 1 0
65
MB91350A Series
(3)Block diagram
Internal data bus (MSB fast) D0 to D7
SI5 to SI7
Initial Value
(MSB fast) D0 to D7 Select transmitting direction Read write
SDR (Serial Data Register)
SO5 to SO7
SCK5 to SCK7
Control circuit
Shift clock counter
Internal clock
2
1
0 SIE SIR BUSY STOP STRT MODE BDS SCE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
PFR Register
66
MB91350A Series
10. 16-bit free-run timer
(1)Description The 16-bit free-running timer consists of a 16-bit up counter, control register, and status register. The count values of this timer are used as the base timer for the output compares and input capture modules. * Four count clock frequencies are available. * An interrupt can be generated at a counter overflow. * The counter can be initialized upon a match with compare register 0 of the output compare unit, depending on the mode.
(2)Register list Timer data register (upper) (TCDT)
15 T15 14 T14 13 T13 12 T12 11 T11 10 T10 9 T9 8 T8
Timer data register (lower) (TCDT)
7 T07 6 T06 5 T05 4 T04 3 T03 2 T02 1 T01 0 T00
Timer control status register (lower) (TCCS)
7 ECLK 6 IVF 5 IVFE 4 STOP 3 MODE 2 CLR 1 CLK1 0 CLK0
(3)Block diagram Interrupt
ECLK IVF IVFE STOP MODE CLR CLK1 CLK0
Divider
Clock select
FRCK
R-bus
Timer data register (TCDT)
Clock
to internal circuit (T15 to T00)
Comparator 0
67
MB91350A Series
11. Input Capture
(1) Description This module detects a rising or falling edge or both edges of an external input signal and stores the 16-bit freerunning timer value in a register. This module stores the 16-bit free-running timer value in a register. In addition, the module can generate an interrupt upon detection of an edge. The input capture module consists of input capture data registers and a control register. Each input capture unit has a corresponding external input pin. * The detection edge of an external input can be selected from among 3 types. Rising edge Falling edge Both edges * An interrupt can be generated upon detection of a valid edge of an external input.
(2) Register list Input capture data register (upper) (IPCP)
15 CP15 14 CP14 13 CP13 12 CP12 11 CP11 10 CP10 9 CP09 8 CP08
Input capture data register (lower) (IPCP)
7 CP07 6 CP06 5 CP05 4 CP04 3 CP03 2 CP02 1 CP01 0 CP00
Capture control register (ICS23)
7 ICP3 6 ICP2 5 ICE3 4 ICE2 3 EG31 2 EG30 1 EG21 0 EG20
Capture control register (ICS01)
7 ICP1 6 ICP0 5 ICE1 4 ICE0 3 EG11 2 EG10 1 EG01 0 EG00
68
MB91350A Series
(3) Block diagram
16-bit timer counter value (T15 to T00) Input capture data register ch (0, 2)
Edge detection
IN0, IN2 Input pin
EG11 R-bus
EG10 EG30
EG01 EG21
EG00 EG20
16-bit timer counter value (T15 to T00) Input capture data register ch (1, 3)
ICP1 ICP3
EG31
Edge detection
IN1, IN3 Input pin
ICE0 ICE2
ICP0 ICP2
ICE1 ICE3
Interrupt Interrupt
69
MB91350A Series
12. Output Compare
(1) Description The output compare module consists of 16-bit compare registers, compare output latch, and control register. When the 16-bit free-running timer value matches the compare register value, the output level is inverted and an interrupt is issued. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 8 channels of this block. This module has the features listed below. * Capable of using the 8 compare registers independently. Output pins and interrupt flags corresponding to the compare registers * A pair of compare registers can be used to control output pins. Using tow compare registers to invert output pins * Capable of setting the initial value for each output pin. * Interrupts can be generated upon a compare match. * The ch0 compare register is used as the compare clear register for the 16-bit free-running timer.
(2)Register list Output compare register(upper) (OCCP)
15 C15 14 C14 13 C13 12 C12 11 C11 10 C10 9 C09 8 C08
Output compare register(lower) (OCCP)
7 C07 6 C06 5 C05 4 C04 3 C03 2 C02 1 C01 0 C00
Output control register(upper) (OCS)
15 14 13 12 CMOD 11 10 9 OTD1 8 OTD0
Output control register(lower) (OCS)
7 ICP1 6 ICP0 5 ICE1 4 ICE0 3 2 1 CST1 0 CST0
70
MB91350A Series
(3) Block diagram
(Only ch0 is used as a free running timer clear register.)
Output compare register
OTD1
OTD0
Compare circuit
R-bus
Output compare register
Compare Output latch
CMOD
OTE0, OTE2, OTE4, OTE6
Output
OTE0 and OTE7 exist in PFRO. There is in PFRO. Compare Output latch
OTE1, OTE3, OTE5, OTE7
Output
Compare circuit
CST1
CST0
ICP1
ICP0
ICE1
ICE0
16-bit free-run timer
Interrupt output Interrupt output
71
MB91350A Series
13. I2C Interface
(1) Description The I2C interface is a serial I/O port supporting the Inter-IC bus, operating as a master/slave device on the I2C bus. It has the following features * Master/slave sending and receiving * Arbitration function * Clock sync function * Slave address and general call address detection function * Ditecting function of transmitting direction * Repeated start condition generation and detection function * Bus error detection function * 10-bit/7-bit slave address * Slave address receive acknowledge control when in master mode * Support for composite slave addresses * Capable of interruption when a transmission or bus error occurs * Standard mode (Max 100K bps)/High speed mode (Max 400K bps) supported
72
MB91350A Series
(2)Register list Bus control register(IBCR) 15 BER Bus status register(IBSR) 7 BB 6 RSC 5 AL 4 LRB 3 TRX 2 AAS 1 GCA 0 ADT 14 BEIE 13 SCC 12 MSS 11 10 9 ACK GCAA INTE 8 INT
10-bit slave address resister (ITBA) 15 7 TA7 14 6 TA6 13 5 TA5 12 4 TA4 11 3 TA3 10 2 TA2 9 TA9 1 TA1 8 TA8 0 TA0
10-bit slave address mask resister(ITMK) 15 ENTB
7 TM7
14 RAL
6 TM6
13
5 TM5
12
4 TM4
11
3 TM3
10
2 TM2
9 TM9
1 TM1
8 TM8
0 TM0
7-bit slave address resister (ISBA) 7 6 SA6 5 SA5 4 SA4 3 SA3 2 SA2 1 SA1 0 SA0
7-bit slave address mask resister (ISMK) 15 14 ENSB SM6 Data register (IDAR)
7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
13 SM5
12 SM4
11 SM3
10 SM2
9 SM1
8 SM0
Clock control register (ICCR)
15 TEST 14 13 EN 12 CS4 11 CS3 10 CS2 9 CS1 8 CS0
Clock disable register (IDBL)
7 6 5 4 3 2 1 0 DBL
73
MB91350A Series
(3) Block diagram
ICCR EN IDBL
Operation enable Clock enable Clock divide 2
2345 32 Sync CLKP
R-bus
DBL ICCR CS4 CS3 CS2 CS1 CS0 IBSR BB
Generating shift clock
Clock selector2 (1/12) Bus busy Start
Shift clock edge changing timing
RSC LRB TRX ADT AL IBCR BER BEIE Last Bit Sending/ receiving
Start stop condition detection Error
First Byte
Arbitration lost detection
SCLI SCLO
Interrupt request
INTE INT IBCR SCC MSS ACK GCAA
IRQ
SDA SDAO
End Start Master ACK enable ACK enable Start stop condition generation
IDAR IBSR AAS GCA ISMK FNSB ITMK ENTB RAL ITBA ITMK ISBA ISMK
Slave Global call Slave address compare
74
MB91350A Series
14. A/D Converter
(1) Description The A/D converter converts the analog input voltage into a digital value. It has the following features: * Conversion time: 1.48 s minimum per channel * Employing serial/parallel conversion type for sample & hold circuit * 10-bit resolution (switchable between 8 and 10 bits) * Program selection of the analog input from among 12 channels * Conversion mode Single conversion mode : Convert 1 selected channel Scan conversion mode : Scan up to 4 channels. * Converted data is stored in the data buffer. * An interrupt request to the CPU can be generated upon completion of A/D conversion. The interrupt can be used to start DMA transfer. * The startup source can be selected from among software, external trigger (falling edge), and reload timer ch2 (rising edge).
(2) Register list
15 87 ADCS2 ADCS1 0
Control status register (ADCS2/ADSC1) Conversion time setting resister (ADCT) Converted data register 0 (ADTH0/ADTL0) Converted data register 1 (ADTH1/ADTL1) Converted data register 2 (ADTH2/ADTL2) Converted data register 3 (ADTH3/ADTL3)
ADTH0 ADTH1 ADTH2 ADTH3
ADTL0 ADTL1 ADTL2 ADTL3
75
MB91350A Series
(3) Block diagram
Analog input
AVCC, AVRH, AVSS/AVRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11
S/H
10 bit A/D Converter
ADT1 ADT2 ADT3
Control logic Interrupt 16-bit reload timer ch2 External input
76
R-bus
M P X
ADT0 M P X
MB91350A Series
15. 8-bit D/A Converter
(1) Description This block contains 2 channels of 8-bit D/A converters. The D/A converter register can be used to control the independent output of each channel. The block has the following features. * Power saving function * 3.3 V Interface
(2) Register list D/A data register 0 to 2(DADR0 to DADR2)
7 DA7 6 DA6 5 DA5 4 DA4 3 DA3 2 DA2 1 DA1 0 DA0
D/A control register 0 to 2 (DACR0 to DACR2)
7 6 5 4 3 2 1 0 DAE
(3) Block diagram
R-bus
D/A control
D/A
D/A
D/A
DAE0 PD STOP
DAE1 PD STOP
DAE2 PD STOP
D/A converter
D/A converter
D/A converter
D/A output 0
D/A output 1
D/A output 2
77
MB91350A Series
16. DMAC (DMA Controller)
(1) Description This module realize direct memory access (DMA) transfer with the FR family device. DMA transfer controlled by this module enables many types of data transfer to be performed at high speed without CPU intervention, thereby improving system performance.
* Hardware configuration
This model consists mainly of the following components: * Independent DMA channels x 5 channels * 5 channels independent access control circuits * 32-bit address register (Supports reloading: 2 per channel) * 16-bit transfer count register (Supports reloading: 1 per channel) * 4-bit block count register (1 per channel) * External transfer request input pins: DREQ0, DREQ1, DREQ2 (ch0, ch1, ch2 only) * External transfer request acceptance output pins: DACK0, DACK1, DACK2 (ch0, ch1,ch2 only) * DMA end output pins: DEOP0, DEOP1, DEOP2 (ch0, ch1, ch2 only) * (ch3 only) fly-by transfer (memory to I/O, I/O to memory) * 2-cycle transfer
* Main function
This module has the following major functions for data transfer: * Supports independent data transfer for multiple channels (5 channels) (1) Priority order (ch0 > ch1 > ch2 > ch3 > ch4) (2) Order can be reversed for ch0 and ch1 (3) DMAC activation triggers * External dedicated pin input (edge detection/level detection: ch0 to ch2 only) * Internal peripheral request (Interrupt request sharing, including external interrupts) * Software request (register write) (4) Transmission mode * Demand transfer, burst transfer, step transfer, or block transfer * Addressing mode: 32-bit full addressing (increment, decrement, or fixed) (address increment can be in the range - 255 to + 255) * Data length: Byte, halfword, or word * Single-shot or reload operation selectable
78
MB91350A Series
(2) Register Description
31 Ch0 control/status register A (DMACA0) register B (DMACB0) Ch1 control/status register A (DMACA1) register B (DMACB1) Ch2 control/status register A (DMACA2) register B (DMACB2) Ch3 control/status register A (DMACA3) register B (DMACB3) Ch4 control/status register A (DMACA4) register B (DMACB4) Overall control register Ch0 transfer source address register (DMACR) (DMASA0) (DMADA0) Ch1 transfer source address register (DMASA1) (DMADA1) Ch2 transfer source address register (DMASA2) (DMADA2) Ch3 transfer source address register (DMASA3) (DMADA3) Ch4 transfer source address register (DMASA4) (DMADA4)
16 15
0
79
MB91350A Series
(3) Block diagram
Counter
DMA transfer request to bus controller
Buffer Selector
Write back
DMA start source select circuit & request acceptance control
Peripheral start request/ Stop input External pin start request/stop input
DTC two-stage register DTCR
Counter
DSS [3:0]
Buffer
Read Write
Priority circuit
To interrupt controller IRQ
ERIR, EDIR
Read/write control Selector
Selector
BLK register
[4:0] MCLREQ
Bus control block
Counter buffer
bus controller
DMA control Selector DSAD two-stage register
SADM, SASZ [7:0] SADR
Address counter
Access Address
Write back
Counter buffer
Selector
DDAD two-stage register
DADM, DASZ [7:0] DADR
Write back
5-channel DMAC block diagram
80
Bus control block
To
DDNO
DDNO register
X-bus
Status transition circuit
Clear peripheral interrupt
TYPE, MOD, WS
MB91350A Series
ELECTRICAL CHARACTERISTICS
1. Abusolute Maximum Rating
Parameter Power supply voltage*1 Analog power supply voltage* Analog reference voltage*1 Input voltage*
1 1 1
Symbol VCC DAVC AVCC AVRH VI VIND VIA VO ICLAMP |ICLAMP| IOL IOLND IOLAV IOLAVND IOL IOLAV IOH IOHAV IOH IOHAV PD Ta TSTG
Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 - 2.0 - 40 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.5 VSS + 5.5 AVCC + 0.5 VCC + 0.5 + 2.0 20 10 20 8 15 100 50 - 10 -4 - 50 - 20 850 + 85 + 125
Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mW C C
Remarks *2 *3 *3 *3 *8 *8 *8 *7 *7 *4
Analog power supply voltage*1
Input voltage (Nch open-drain) * Analog pin input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current
"L" level maximum output current "H" level maximum output current (Nch open-drain) "L" level average output current "H" level average output current (Nch open-drain) "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
*5
*6 *4 *5
*6
*1 : The parameter is based on VSS = DAVS = AVSS = 0 V. *2 : VCC must not be lower than VSS - 0.3 V. *3 : Be careful not to exceed "VCC + 0.3 V", for example, when the power is turned on. *4 : The maximum output current is the peak value for a single pin. *5 : The average output current is the average current for a single pin over a period of 100 ms. *6 : The total average output current is the average current for all pins over a period of 100 ms.
81
MB91350A Series
*7 : * Relevant pins: Port2, 3, 4, 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P and AN (A/D input) , * Use within recommended operating conditions. * Use at DC voltage (current). * The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. * The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that, when the microcontroller drive current is low as in low power consumption mode, the + B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. * Note that, if the + B input exists when the microcontroller is off (not fixed at 0 V), power is supplied through the pin, possibly causing the microcontroller to operate imperfectly. * Note that, if the + B input exists when the power supply is turned on, power is supplied through the pin, possibly resulting in a power-supply voltage at which a power-on reset does not work. * Be careful not to let the + B input pin open. * Note that the analog I/O pins (such as the LCD drive and comparator input pins) other than the A/D input pin cannot input + B. * Sample recommended circuits:
* Input/output equivalent circuits
Protective diode
Vcc
+ B input (0 V to 16 V)
Limiting resistance
Pch
Nch
R
*8: VI should not exceed the specified ratings. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
82
MB91350A Series
2. Recommended Operating Conditions
(VSS = DAVS = AVSS = 0 V) Parameter Power supply voltage Analog power supply voltage Analog reference voltage Operating temperature Symbol VCC VCC DAVC AVCC AVRH Ta Value Min 3.0 3.0 VSS - 0.3 VSS - 0.3 AVSS - 40 Max 3.6 3.6 VSS + 3.6 VSS + 3.6 AVCC + 85 Unit V V V V C Remarks At normal operating hold RAM status at stop
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
83
MB91350A Series
3. DC Characteristics
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter Symbol VIH Pin Port 2, 3, 4, 5, 6, 9, A, B, C Port 8, G, H, I, M, N, O, P, MD0, MD1, MD2, INIT, NMI Port J, K, L Port 2, 3, 4, 5, 6, 9, A, B, C Port 8, G, H, I, M, N, O, P, MD0, MD1, MD2, INIT, NMI Port J, K, L Conditions Value Min VCC x 0.65 Typ Max VCC - 0.3 Unit Remarks
V
"H" level input voltage
VIHS
VCC x 0.8
VCC - 0.3
V
Hysteresis input
VIHST
VCC x 0.8
5.25
V
Hysteresis input with stand voltage of 5 V
VIL
VSS
VCC x 0.25
V
"L" level input voltage
VILS
VSS
VCC x 0.2
V
Hysteresis input
VILST
VSS
VCC x 0.2
V
Hysteresis input with stand voltage of 5 V
"H" level output voltage
VOH
Port 2, 3, 4, 5, 6, 8, 9, A, VCC = 3.0 V B, C, G, H, I, IOH = - 4.0 mA J, K, M, N, O, P Port 2, 3, 4, 5, 6, 8, 9, A, VCC = 3.0 V B, C, G, H, I, IOL = 4.0 mA J, K, M, N, O, P Port L VCC = 3.0 V IOL = 15.0 mA VCC = 3.6 V 0VCC - 0.5
VCC
V
"L" level output voltage
VOL1
VSS
0.4
V
VOL2 Input leak current (High-Z output Leakage current) Pull-up resistance
VSS
0.4
V
Nch open-drain
ILI
All input pin
-5
+5
A
RUP
setting pin VCC = 3.6 V INIT, Pull up VI = 0.45 V
25
50
200
k (Continued)
84
MB91350A Series
(Continued) Symbol (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Pin Conditions Value Min Typ Max Unit Remarks
Parameter
ICC
fC = 12.5 MHz VCC = 3.3 V
160
220
Multiply by 4 CLKB : 50 MHz mA CLKT : 25 MHz When operating at 25 MHz Sleep mA When operating at 25 MHz A at stop
ICCS
fC = 12.5 MHz VCC = 3.3 V Ta = + 25 C VCC = 3.3 V VCC Ta = + 25 C fC = 32.768 kHz VCC = 3.3 V Ta = + 25 C fC = 32.768 kHz VCC = 3.3 V Ta = + 25 C fC = 32.768 kHz VCC = 3.3 V Other than VCC, VSS, AVCC, AVSS, DAVC, DAVS

100
140
Power supply current
ICCH
1
100
ICCL
0.3
3.0
Sub RUN CLKB : 32.768 kHz mA CLKT : 32.768 kHz When operating at 32.768 kHz Sub sleep mA When operating at 32.768 kHz A at watch mode operating (Main Off, STOP)
ICCLS
0.2
2.0
ICCT
5
120
Input capacitance
CIH
5
15
pF
85
MB91350A Series
4. AC Characteristics
(1) Clock timing (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter Clock frequency Clock cycle time Symbol fC Pin X0 X1 X0 X1 X0 X1 80 100 ns Conditions Value Min 10 Typ Max 12.5 Unit MHz Remarks Main PLL (When operating at max internal frequency (50 MHz) = 12.5 MHz self-oscillation with x 4 PLL)
tC
Clock frequency Internal operating clock frequency
fC fCP fCPP fCPT tCP
When a minimum value of 12.5 MHz is input as the X0 clock frequency and x 4 multiplication is set for the PLL of the oscillator circuit PWH/tc PWL/tc When a standard value of 32.768 kHz is input as the X0A clock frequency
10 2.94* 2.94* 2.94* 20 40 40 30 28.6 40
32.768 30.51
25 50 25 25 340* 340* 340* 35 33.3 60 32
Main self-oscillation MHz (frequency-halved input) MHz CPU MHz Peripheral MHz External bus ns ns ns kHz s % CPU Peripheral External bus SUB self-oscillation
Internal operating clock cycle time Clock frequency Clock cycle time Input clock palse width Internal operating clock frequency Internal operating clock cycle time
tCPP tCPT fC tC fCP, fCPP, fCPT tCP, tCPP, tCPT
X0A X1A X0A X1A X0 X1
2*
kHz
30.51
500*
s
* : The values assume a gear cycle of 1/16.
86
MB91350A Series
* Conditions for measuring the clock timing ratings
tC 0.8 VCC 0.2 VCC
Output pin
C = 50 pF
PWH tCF
PWL tCR
* Operation Assurance Range
VCC (V)
Operation Assurance Range (Ta = - 40C to + 85C) fCPP is represented by the shaded area. Power supply
3.6
3.0
0 2.94
25
50
fCP, fCPP (MHz)
Internal clock
87
MB91350A Series
* External/internal clock setting range
(MHz) fCP 50
Oscillation input clock fC = 12.5 MHz
CPU (CLKB) :
Internal clock
Peripheral External bus(CLKT) :
fCPP, fCPT 25
12.5
CPU :
4:4 2:2 1:2
Notes : * When the PLL is used, the external clock input must fall between 10.0 and 12.5 MHz. * Set the PLL oscillation stabilization wait time longer than 454.5 s. The internal clock gear setting should not exceed the relevant value in the table in "(1) Clock timing ratings".
88
MB91350A Series
(2)Clock output timing (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter Cycle time SYSCLK SYSCLK SYSCLK SYSCLK Symbol tCYC tCHCL tCLCH Pin MCLK, SYSCLK MCLK, SYSCLK MCLK, SYSCLK Conditions Value Min tCPT tCYC - 5 tCYC - 5 Max tCYC + 5 tCYC + 5 Unit ns ns ns Remarks *1 *2 *3
*1 : tCYC is the frequency of one clock cycle after gearing. *2 : The following ratings are for the gear ratio set to x 1. For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation. (1 / 2 x 1 / n ) x tCYC - 10 *3 : The following rating are for the gear ratio set to x 1. Note : tCPT indicates the internal operating clock cycle time. See "(1) Clock timing". In the following AC ratings, MCLK is equivalent to SYSCLK.
tCYC tCHCL VOH tCLCH VOH
MCLK SYSCLK
VOL
(3) Reset and hardware standby ratings (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter INIT input time (at power-on) INIT input time (other than at power-on) Symbol Pin Conditions Value Min tC x 10 tINTL INIT tC x 10 ns Max Unit ns Remarks
Note : tC indicates the clock cycle time. See "(1) Clock timing".
tINTL
INIT
0.2 VCC
89
MB91350A Series
(4) Normal bus access read/write operation (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter CS0 to CS3 setup CS0 to CS3 hold Symbol tCSLCH tCSDLCH tCHCSH tASCH Address setup tASWL tASRL tCHAX Address hold tWHAX tRHAX Valid address Valid data input time WR0, WR1 delay time WR0, WR1 delay time WR0, WR1 minimum pulse width Data setup WRx WRx Data hold time RD delay time RD delay time RD Valid data input time Data setup RD Time RD Data hold time RD minimum pulse width AS setup AS hold tAVDV tCHWL tCHWH tWLWH tDSWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tCHASH RD MCLK, AS RD, D31 to D16 MCLK, A23 to A00 WR0, WR1, A23 to A00 RD, A23 to A00 MCLK, A23 to A00 WR0, WR1, A23 to A00 RD, A23 to A00 A23 to A00, D31 to D16 MCLK, WR0, WR1 WR0, WR1 WR0, WR1, D31 to D16 MCLK, RD Pin Conditions Value Min 3 -3 3 3 3 3 3 3 3 tCYC - 5 tCYC 3 10 0 tCYC - 5 3 3 Max tCYC/2 + 6 tCYC/2 + 6 3 / 2 x tCYC - 15 6 6 6 6 tCYC - 10 tCYC/2 + 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *1 *2
Remarks
AWRxL*3 : W02 = 0 MCLK, AWR0L : W02 = 1 CS0 to CS3
*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC x the number of cycles added for the delay) to this rating. *2 : The following ratings are for the gear ratio set to x 1. For the ratings when the gear ratio is set to between 1/2 to 1/16, substitute 1/2 to 1/16 for n in the following equation. Calculation expression: 3/(2n) x tCYC - 15 *3 : AWRxL : Area Wait Register Note : tCYC indicates the cycle time. See "(2) Clock output timing". 90
MB91350A Series
tCYC BA1 VOH VOH VOH VOH
MCLK
tASLCH
tCHASH VOH
AS (LBA)
VOL
tCSLCH
tCHCSH VOH
CS0 to CS3
VOL
tASCH VOH VOL
tCHAX VOH VOL
A23 to A00
tCHRL
tCHRH tRLRH VOH VOL
RD
tASRL tRLDV tDSRH tAVDV tRHDX
tRHAX
D31 to D16
VOH VOL tCHWL tWLWH tCHWH VOH tASWL VOL
VOH VOL
WR0, WR1
tWHAX tWHDX
tDSWH VOH VOL
D31 to D16
write
VOH VOL
91
MB91350A Series
(5) Multiplex bus access read/write operation (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter AD15 to AD0 Address AUDI setup time MCLK MCLK AD15 to AD0 Address AUDI Hold Time AD15 to AD0 Address AUDI setup time AS AS AD15 to AD0 Address AUDI Hold Time Symbol Pin Conditions Value Min 3 MCLK, D31 to D16 tCHAX tASASH AS, D31 to D16 12 tCYC - 3 tCYC + 3 ns 3 tCYC/2 + 6 ns Max Unit Remarks
tASCH
ns
tASHAX
ns
Notes : * This rating is not guaranteed when the CSRD/WR, and setup delay setting by AWR: bit 1 is "0". * Beside This rating, normal bus interface ratings are applicable. * tCYC indicates the cycle time. See "(2) Clock output timing".
tCYC BA1 VOH VOH VOH VOH
MCLK
VOH
AS
VOL tASASH tASCH VOH VOL tASHAX tCHAX VOH VOL
D31 to D16
92
MB91350A Series
(6) Ready input timings (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to +85C) Parameter RDY setup time MCLK MCLK RDY hold time Symbol tRDYS tRDYH Pin MCLK, RDY MCLK, RDY Conditions Value Min 15 0 Max Unit ns ns Remarks
tCYC
VOH
VOH VOL
MCLK
VOL
tRDYS
tRDYH
tRDYS
tRDYH
RDY
with wait
VOL
VOH VOL
VOH
without wait
RDY
VOH VOL
VOH VOL
93
MB91350A Series
(7) Hold timing (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter BRQ setup time MCLK MCLK BRQ AUDI Hold Time BGRNT delay time BGRNT delay time Pin floating BGRNT time BGRNT Pin valid time Symbol tBRQS tBRQH tCHBGL tCHBGH tXZBGL tBGHXV Pin Conditions Value Min 15 0 tCYC/2 - 6 tCYC/2 - 6 tCYC - 10 tCYC - 10 tCYC/2 + 6 tCYC/2 + 6 tCYC + 10 tCYC + 10 ns ns ns ns ns Max Unit ns Remarks
MCLK, BRQ MCLK, BGRNT BGRNT, D31 to D16, A23 to A00, CS3 to CS0*
* : These are applied to only the case that SREN bit of area select register (ACR) is set to "1". Notes : * It takes 1 cycle or more from when BRQ is captured until BGRNT changes. * tCYC indicates the cycle time. See "(2) Clock output timing".
tCYC VOH VOH VOH VOH
MCLK
tBRQS
tBRQH VOL VOH tCHBGL tCHBGH VOH tBGHXV
BRQ
BGRNT
tXZBGL
VOL
D31 to D16, A23 to A00, CS3 to CS0 *
High-Z
* : These are applied to only the case that SREN bit of area select register (ACR) is set to "1".
94
MB91350A Series
(8) UART, SIO timing (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter Serial clock cycle time SCK BGRNT delay time Valid SI SCK SCK valid SIN hold time Serial clock H Pulse Width Serial clock L Pulse Width SCK SO delay time Valid SI SCK SCK valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0 to SCK7 SCK0 to SCK7, SO0 to SO7 Internal shift SCK0 to SCK7, clock mode SI0 to SI7 SCK0 to SCK7, SI0 to SI7 SCK0 to SCK7 SCK0 to SCK7 SCK0 to SCK7, External SO0 to SO7 shift clock SCK0 to SCK7, mode SI0 to SI7 SCK0 to SCK7, SI0 to SI7 Conditions Value Min 8 tCPP - 80 100 60 4 tCPP 4 tCPP 60 60 Max + 80 150 Unit ns ns ns ns ns ns ns ns ns Remarks
Notes : * Above rating is for CLK synchronous mode. * tCPP indicates the peripheral clock cycle time. See "(1) Clock timing".
* Internal shift clock mode
tSCYC
SCK0 to SCK7
VOH VOL tSLOV VOL
SO0 to SO7
VOH VOL tIVSH VOH VOL tSHIX VOH VOL
SI0 to SI7
* External shift clock mode
tSLSH
tSHSL VOH VOL VOL
SCK0 to SCK7
VOL tSLOV
SO0 to SO7
VOH VOL tIVSH tSHIX VOH VOL
SI0 to SI7
VOH VOL
95
MB91350A Series
(9) Free-run timer clock, PPG timer input timing (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter Symbol Pin FRCK, TRG0 to TRG5, AIN0 to AIN1, BIN0 to BIN1, ZIN0 to ZIN1 Conditions Value Min Max Unit Remarks
Input pulse width
tTIWH tTIWL
2 tCPP
ns
Note : tCPP indicates the peripheral clock cycle time. See "(1) Clock timing".
tTIWH
tTIWL
(10) Trigger input timing (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter A/D activation trigger input time input capture input trigger Symbol tATGX tINP Pin ATG IN0 to IN3 Conditions Value Min 5 tCPP 5 tCPP Max Unit ns ns Remarks
Note : tCPP indicates the peripheral clock cycle time. See "(1) Clock timing".
tATGX, tINP
ATG, IN0 to IN3
96
MB91350A Series
(11)DMA controller timing * For edge detection (block/step transfer mode,burst transfer mode) (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter DREQ Input pulse width DREQ Input pulse width Symbol tDRWL tDSWH Pin DREQ 0 to DREQ2 DSTP 0 to DSTP2 Conditions Value Min 2 tCYC* 2 tCYC* Max Unit Remarks ns ns
* : tCYC becomes tCP when fCPT is greater than fCP . * For level detection (demand transfer mode) (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter DREQ setup time DREQ Hold Time DSTP setup time DSTP Hold Time Symbol tDRS tDRH tDSTPS tDSTPH Pin MCLK, DREQ 0 to DREQ2 MCLK, DREQ 0 to DREQ2 MCLK, DSTP 0 to DSTP2 MCLK,DSTP 0 to DSTP2 Conditions Value Min 15 0.0 15 0.0 Max Unit Remarks ns ns ns ns
* Common operation mode (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter Symbol tDALCH DACK delay time tDADLCH tCHDAH tDELCH DEOP delay time tDEDLCH tCHDEH IORD delay time IOWR delay time IORD minimum pulse width IOWR minimum pulse width * : AWRxL: Area Wait Register. Note : tCYC indicates the cycle time. See "(2) Clock output timing". 97 tCHIRL tCHIRH tCHIWL tCHIWH tIRLIRH tIWLIWH MCLK, IORD MCLK, IOWR IORD IOWR MCLK, DEOP 0 to DEOP2 MCLK, DACK 0 to DACK2 Pin Conditions AWRxL* : W02 = 0 AWR0L : W02 = 1 AWR0L : W02 = 0 AWRxL* : W02 = 1 Value Min 3 -3 3 -3 12 12 Max 6 6 tCYC/2 + 6 6 6 6 tCYC/2 + 6 6 6 6 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks CS timing FR30 compatible CS timing FR30 compatible CS timing FR30 compatible CS timing FR30 compatible CS timing FR30 compatible CS timing FR30 compatible
MB91350A Series
tCYC
VOH
VOH VOL tDRWL tDRS tDRH VOH VOL tDSWH tDSTPS VOH VOL tCHIRL tIRLIRH tCHIRH VOH VOL tCHIWL tIWLIWH VOH tCHIWH tDSTPH VOL
MCLK
VOL
DREQ0 to DREQ2
DSTP0 to DSTP2
IORD
IOWR
VOL
RD, WRn
VOH VOL
Chip select timing
DACK0 to DACK2
tDALCH tDADLCH
tCHDAH VOH
VOL tDELCH tDEDLCH
tCHDEH VOH
DEOP0 to DEOP2
FR30 compatible timing
VOL
tDALCH tDADLCH VOL tDELCH tDEDLCH
tCHDAH VOH
DACK0 to DACK2
tCHDEH VOH
DEOP0 to DEOP2
VOL
98
MB91350A Series
(12) I2C Timing (VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = - 40C to + 85C) Parameter SCL clock frequency*4 Hold time (repeated) START condition SDASCL "L" width of the SCL clock "H" width of the SCL clock Set-up time for a repeated START condition SCLSDA Data hold time SCLSDA Data set-up time SDASCL Set-up time for STOP condition SCLSDA Bus free time between a STOP and START condition Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS R = 1.0 k, C = 50 pF*1 Condition Standard-mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 Max 100 3.45*2 Fast-mode*4 Min 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 Max 400 0.9*3 Unit kHz s s s s s ns s s
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT only has to be met if the device does not stretch the "L" width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT 250 ns must then be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA tLOW SCL tHIGH tHDSTA tHDDAT tSUSTA tSUSTO tSUDAT tHDSTA tBUS
99
MB91350A Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, AVRH = 3.0 V to 3.6 V, Ta = - 40C to + 85C) Parameter Resolution Total error*
1 1
Symbol
Pin AN11 to AN0
Value Min - 5.0 - 3.5 - 2.5
AVRL - 2.0
Typ
AVRL + 1.0 AVRH + 1.5
Max 10 + 5.0 + 3.5 + 2.5
AVRL + 6.0 AVRH + 3.0
Unit bit LSB LSB LSB LSB LSB s mA A A A pF LSB
Remarks
IA IAH IR IRH
Nonlinear error*
Differential linear error*1 Zero transition voltage* Full-transition voltage*1 Conversion time Analog power supply current (analog + digital) Reference power supply current (between AVRH and AVRL) Analog input capacitance Interchannel disparity
1
AVcc = 3.3 V, AVRH = 3.3 V
AN11 AVRH - 5.5 to AN0 AVCC 1.48*2 AN11 to AN0 AN11 to AN0
8 470 40
300 5 10 4
At stop AVRH = 3.0 V, AVRL = 0.0 V At stop
AVRH
*1: Measured in the CPU sleep state *2: When the peripheral resource clock frequency is 25.0 MHz, set the Conversion Time Setting Register (ADCT) to a value equal to or greater than 5334H. Set each bit as follow : Sampling time : SAMP3 to SAMP0 5H Conversion time a : CV03 to CV0 3H Conversion time b : CV13 to CV0 3H Conversion time c : CV23 to CV0 4H
100
MB91350A Series
* About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. * Analog input circuit model
R
Analog input
C
Comparator
During Sampling : ON R 0.18 k (Max) 0.18 k (Max) 0.18 k (Max) C 63.0 pF (Max) 39.0 pF (Max) 39.0 pF (Max)
Note : The values are reference values.
MB91355A MB91F355A MB91F356B
* To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
* The relationship between the external impedance and minimum sampling time (External impedance = 0 k to 100 k)
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 MB91F355A/MB91F356B
(External impedance = 0 k to 20 k)
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 MB91F355A/MB91F356B
External impedance [k]
External impedance [k]
MB91355A
MB91355A
20
25
30
35
4
5
6
7
8
Minimum sampling time [s]
Minimum sampling time [s]
* If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.
* About errors As |AVRH-AVSS| becomes smaller, values of relative errors grow larger.
101
MB91350A Series
Definition of A/D Converter Terms
* Resolution
Analog variation that is recognized by an A/D converter.
* Linearity error
Zero transition point ( "0000000000" - "0000000001") and full-scale transition point Difference between the line connected ("1111111110" - "1111111111") and actual conversion characteristics.
* Differential linear error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Linearity error
3FFH 3FEH 3FDH {1 LSB' (N - 1) + VOT}
Differential linear error
Actual conversion characteristic
N+1
Actual conversion characteristic
VFST
(measurement value)
Digital output
Digital output
Ideal characteristics
N
004H 003H 002H 001H
VNT
(measurement value)
N-1
V(N+1)T
(measurement value)
Actual conversion characteristic Ideal characteristics VOT (measurement value)
VNT
N-2
(measurement value) Actual conversion characteristic
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
Linear error in digital output N = VNT - {1 LSB' x (N - 1) + {VOT} [LSB] 1 LSB' Differential linear error in digital output N = 1 LSB = VFST - VOT 1022 [V] V (N + 1) T - VNT 1 LSB' - 1 [LSB]
VOT: A voltage at which digital output transitions from (000)H to (001)H. VFST: A voltage at which digital output transitions from (3FE)H to (3FF)H. VNT: A voltage at which digital output transitions from (N - 1) to N.
102
MB91350A Series
* Total error
This error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error.
Total error
3FFH 3FEH 3FDH
Actual conversion characteristic
1.5 LSB'
Digital output
{1 LSB' (N - 1) + 0.5 LSB'}
004H 003H 002H 001H 0.5 LSB' AVSS AVRH
(measurement value)
VNT
Actual characteristics
Ideal characteristics
Analog input 1LS' (Ideal value) 1 = AVRH - AVSS 1024
[V]
Total error of digital output N =
VNT - {1 LSB' x (N - 1) x {0.5 LSB'} 1 LSB'
VNT: A voltage at which digital output transitions from (N + 1) to (N). VOT'(Ideal value) = AVSS + {0.5 LSB' [V] VFST'(Ideal value) = AVRH - 1.5 LSB' [V]
103
MB91350A Series
6. Electrical Characteristics for the D/A Converter
(VCC = DAVC = 3.0 V = 3.6 V, VSS = DAVS = 0 V, Ta = - 40C to + 85C) Parameter Resolution Nonlinear error Differential linear error Convertion speed Output high impedance
Symbol
Pin DA0 to DA2
Value Min - 2.0 - 1.0 2.0 Typ 0.6 3.0 2.9 40 0.1 Max 8 + 2.0 + 1.0 3.8 460*
Unit bit LSB LSB s s k A A A
Remarks

When the output is unloaded When the output is unloaded When load capacitance (CL) = 20 pF When load capacitance (CL) = 100 pF
10 s conversion when the output is unloaded Input digital code When fixed at 7AH or 85H At power-down
Analog current
IADA IADAH
DAVC

* : This D/A converter varies in current consumption depending on each input digital code. This rating indicates the current consumption when the digital code that maximizes current consumption is input.
104
MB91350A Series
FLASH MEMORY WRITE/ERASE CHARACTERISTICS
Parameter Sector erase time Chip erase time Half word (16-bit width) writing time Write/erase cycle Flash data retention time Average Ta = +85C Ta = +25 C, VCC = 3.3 V Condition Value Min 20 Typ 1 8 16 10,000 Max 15 3,600 Unit s s s cycle year * Remarks Excludes 00H programming prior erasure. Excludes 00H programming prior erasure. Excludes system-level overhead.
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85C).
105
MB91350A Series
EXAMPLE CHARACTERISTICS
(1) "H" level output voltage (2) "L" level output voltage
Ta = +25 C
VOH - VCC
4
VOL1 - VCC
500 400 300 200 100 0 2.7 3.0 3.3
Ta = +25 C
VOH [V]
3 2 1 0 2.7 3.0 3.3 3.6 3.9
VOL1 [mV]
3.6
3.9
VCC [V]
(3) "L" level output voltage (Nch open-drain) (4) Input leak current
VCC [V]
VOL2 - VCC
500 400 300 200 100 0 2.7 3.0 3.3
Ta = +25 C
ILI - VCC
6 4 2 0
Ta = +25 C
VOL2 [mV]
ILI [A]
3.6 3.9
-2 -4 -6
2.7 3.0 3.3 3.6 3.9
VCC [V]
(5) Pull-up resistance
VCC [V]
RUP - VCC
200 160 120 80 40 0 2.7 3.0 3.3
Ta = +25 C
RUP [k]
3.6
3.9
VCC [V]
(Continued)
106
MB91350A Series
(6) Power supply current
ICC - VCC
300 250 200 150 100 50 0 2.7 Ta = +25 C, fCP = 50 MHz, fCCP = fCPT = 25 MHz
300 250 200 150 100 50 0
(7) Power supply current
ICC - fC
Ta = +25 C, VCC = 3.3 V, fCP = 4 x fC (multiplied by 4)
ICC [mA]
3.0
3.3
3.6
3.9
ICC [mA]
1
10
100
VCC [V]
fC [MHz]
(8) Power supply current at sleep
ICCS - VCC
300 250 200 150 100 50 0 2.7 Ta = +25 C, fCP = 50 MHz, fCCP = fCPT = 25 MHz
(9) Power supply current at sleep
ICCS - fC
300 250 200 150 100 50 0 Ta = +25 C, VCC = 3.3 V, fCP = 4 x fC (multiplied by 4)
ICCS [mA]
3.0
3.3
3.6
3.9
ICCS [mA]
1
10
100
VCC [V]
fC [MHz]
(10) Power supply current at stop
ICCH - VCC
100 80 60 40 20 0 Ta = +25 C
(11) Sub RUN power supply current
ICCL - VCC
500 400 Ta = +25 C, fCP = 32 kHz, fCCP = fCPT = 32 kHz
ICCH [A]
ICCL [A]
2.7 3.0 3.3 3.6 3.9
300 200 100 0 2.7 3.0 3.3 3.6 3.9
-20 VCC [V]
VCC [V]
(12) Sub sleep power supply current
ICCLS - VCC
500 Ta = +25 C, fCP = 32 kHz, fCCP = fCPT = 32 kHz
(13) Watch mode power supply current
ICCT - VCC
100 80 60 40 20 0 Ta = +25 C, fCP = 32 kHz, fCCP = fCPT = 32 kHz
ICCLS [A]
400 300 200 100 0 2.7 3.0 3.3 3.6 3.9
ICCT [A]
-20
2.7 3.0 3.3 3.6 3.9
VCC [V]
VCC [V]
(Continued) 107
MB91350A Series
(Continued) (14) A/D converter power supply current
(15) A/D converter reference power supply voltage
IA - VCC
10 8
Ta = +25 C
IR - VCC
1000 800
Ta = +25 C
IA [mA]
IR [A]
3.0 3.3 3.6 3.9
6 4 2 0 2.7
600 400 200 0 2.7 3.0 3.3 3.6 3.9
VCC [V]
(16) A/D converter power supply current at stop
VCC [V]
(17) A/D converter reference power supply current at stop
IAH - VCC
20
Ta = +25 C
IRH - VCC
20
Ta = +25 C
IAH [A]
IRH [A]
10 0
10 0
-10
2.7 3.0 3.3 3.6 3.9
-10
2.7 3.0 3.3 3.6 3.9
VCC [V]
(18) D/A converter power supply current < per 1 channel >
VCC [V]
(19) D/A converter power supply current at power down
IADA - VCC
500 400
Ta = +25 C
IADAH - VCC
20
Ta = +25 C
IADAH [A]
IADA [A]
300 200 100 0 2.7 3.0 3.3 3.6 3.9
10 0
-10
2.7 3.0 3.3 3.6 3.9
VCC [V]
VCC [V]
108
MB91350A Series
ORDERING INFORMATION
Part number MB91F355APMT-002 MB91F356BPMT MB91355APMT MB91354APMT Package 176-pin plastic LQFP (FPT-176P-M02) 176-pin plastic LQFP (FPT-176P-M02) 176-pin plastic LQFP (FPT-176P-M02) 176-pin plastic LQFP (FPT-176P-M02) Remarks Lead-free Package Lead-free Package Lead-free Package Lead-free Package
109
MB91350A Series
PACKAGE DIMENSION
176-pin plastic LQFP (FPT-176P-M02) Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25 (.010) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
26.000.20(1.024.008)SQ
* 24.000.10(.945.004)SQ
0.1450.055 (.006.002)
132 89
133
88
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0~8 INDEX 0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.25(.010)
176
45
"A" LEAD No.
1 44
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
C
2003 FUJITSU LIMITED F176006S-c-4-6
Dimensions in mm (inches). Note: The values in parentheses are reference values.
110
MB91350A Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0505 (c) 2005 FUJITSU LIMITED Printed in Japan

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